ZYNQ QSPI Controller Application Note

ZYNQ QSPI Controller Application Note

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1 ZYNQ QSPI Controller

The ZYNQ QSPI controller supports three modes: I/O mode, linear address mode, and traditional SPI mode, where the linear address mode dual-chip option supports a maximum linear address space of 32MB and can be read by PS DMA.

1.1 Linear Address mode

Linear address mode can only be read from QSPI Flash. When configuring QSPI boot, the boot ROM works in linear address mode, and the clock is accessed by arm for the crystal clock, so the frequency cannot be greater than the maximum access clock frequency of the flash when the crystal oscillator is selected.

The linear address mode IO can be configured as a single-chip 4bit interface, a dual-chip select 8bit parallel interface and a dual-chip select stacked interface, a monolithic device must be connected to the QSPI0. Single-chip QSPI flash linear address mapping space for 0XFC00_0000~0XFCFF_FFFF, if the use of two pieces, must be the same manufacturer, the same guarantee agreement, in the configuration of dual-chip 8bit parallel interface, two flash must be the same capacity of the same manufacturer device, Guaranteed access is fully synchronized and the addressing space is 0xfc00_0000~0xfdff_ffff.

When configured as a dual-chip select stacked interface, the capacity can be different, but must be the same protocol as the device. However, the first piece of the device recommends the use of a 128Mb device, so there is no address empty area. The read operation of the linear address pattern is extremely simple, setting qspi.config_reg[man_start_en] and qspi while ensuring that Txfifo and Rxfifo are empty. CONFIG_REG[PCS] is 0,QSPI. Lqspi_cfg. [Lq_mode] is 1.

1.2 IO Mode

In IO mode, commands, addresses, and data that access QSPI Flash are written to the FIFO by the user software organization as specified in the SPI Flash data sheet, and the controller is responsible for serializing it from the bus. In IO mode, you can choose both automatic and manual modes of operation, and manual mode with automatic chip selection and manual selection of two modes. There are some limitations in automatic mode from sending data to receiving data, so it is more manual mode in actual use.

The QSPI controller provides four TXD registers that can write data to the FIFO, as shown in table 1 below.

Table 1 TXD Registers

Register	Data format				Function
	[31:24]	[23:16]	[15:0]	[7:0]
TXD0	Data3	Data2	Data1	Data0/cmd	Transfer 1byte Command 3byte data or 4byte data
TXD1	Keep	Keep	Keep	Data0/cmd	Transfer 1byte Command
TXD2	Keep	Keep	Data1	Data0/cmd	Transfer 1byte commands and 1byte data
TXD3	Keep	Data2	Data1	Data0/cmd	Transfer 1byte commands and 2byte data

This provides a rich selection, either by word, by byte, by double-byte three-byte, but note that it is necessary to wait for the FIFO to be empty when switching between different registers. Txfifo and Rxfifo Use the same gate clock, so for each byte, including the command and address, each byte is fetched from Txfifo, and one of its own data is written to the Rxfifo.

In order to read from the SPI Flash data, the software in addition to write the relevant commands, addresses, patterns, dummy, but also must write to Txfifo and read the number of data equal to dummy data, so that the controller will write Rxfifo clock.

It is important to note that in IO mode, the controller automatically recognizes the user instruction, the first instruction that writes the FIFO when the controller is enabled, and the chip is valid, is considered by the controller as a command, the command is always sent through the data line D0, the COMMAND + data is up to 4 bytes, that is, when the read and write command is issued, The valid address bit is always 3 bytes and can only access the 16MB address space.

The command to automatically identify the meaning of the controller is shown in table 2.

table 2 commands for the controller to automatically identify meanings

Command	Meaning	Describe
READ	Read data, cmd=0x03	The order is sent through the D0; the data is received through D0
Fast_read	Fast read data, CMD=0XB	The order is sent through the D0; the data is received through D0
DOR	Dual IO read data, cmd=0x3b	The order is sent through the D0; data is received via d[1:0]
QOR	Four IO line read data, cmd=0x6b	The order is sent through the D0; data is received via d[3:0]
DIOR	Dual IO command, four IO data, CMD=BB	Command sent via d[1:0], data received via d[3:0]
Qior	Quad IO command, four IO data, Cmd=eb	Command sent via d[3:0], data received via d[3:0]
Pp	Page programming commands, cmd=02	The order is sent through the D0, and the data is sent through D0
QPP	Four IO page programming commands, cmd=32 or 38	Command issued via D0, data via d0[3:0]

The controller supports only the commands shown in table 2 and automatically switches the operating mode of the controller, either in linear address mode or IO mode access QSPI. In addition to the commands listed in table 2, the controllers are issued and received by default via D0.

2 QSPI Flash Selection

The ZYNQ QSPI Flash Controller does not support all QSPI flash devices, so when selecting QSPI flash you must meet:

① Support qor command: bootrom default mode;

The ② supports 3-byte address mode: The default maximum support is 16MB, which is still accessible through the 3-byte address mode after the 16MB portion is set through the address register.

QSPI Flash devices are not supported as described in section UG585 12.2.6.

2.1 QSPI Flash Operation example

Take Spotlight's n25q512 QSPI Flash as an example, briefly explain the main points:

The n25q512 Qspiflash supports the extended, dual, and quad three SPI protocol modes, the default is extended mode, and the default mode is matched to the ZYNQ QSPI Controller Access Protocol.

n25q512 Qspiflash A total of 512Mb density, divided into 4 banks, each bank density of 16MB, can be accessed through the extended address register or switch to 4-byte addressing mode to more than 16MB of space. Because ZYNQ QSPI Flash supports only 3-byte address patterns, access to the high address space is achieved by switching the extended address register. There is a certain risk in this way, that is, bootrom can only access the low 16MB space, in order to avoid the image to write to the high address space, every time with Xilinx tools to write flash before burning will have to restart the power cycle, so that flash extended Addressregister reverts to the default state.

n25q512 Qspiflash must issue a write enable command (06H) before Erase, program, and access the internal register, and must read the FlagStatus register after the Erase, program command is issued.

n25q512 Qspiflash, Erase can be a sub-page wipe (4KB), page erase (64KB), and Die Erase (32MB). A page size is 256B, so each program command can write only 256 bytes of data.

3 Considerations for Boot devices

When using QSPI flash you need to note:

①bootrom can only access low 16M (single ss) or low 32M (dual ss), so the mirror must be stored under accessible space;

② single SS, the starting device must be hung on the Qspi control 0;

③ dual SS Parallel 8bit mode when the Bootrom search step is 64KB, its mode is 32KB, so in order to reduce the search time, the boot image should preferably start at address 0.

4 Resources

Xilinx offers bare-metal board-level support packages, Uboot drives, and Linux drivers.

①xilinx Board-level support package instances:

/sdk/2015.2/data/embeddedsw/xilinxprocessoriplib/drivers/qspips_v3_2/examples;

②uboot Drive:/u-boot-xlnx-master/drivers/spi/zynq_qspi.c

③linux driver:/dirvers/spi/zynq-qspi.c, description document in:

Www.wiki.xilinx.com/Zynq+QSPI+Driver

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Copyright NOTICE: This article for Bo Master original article, without Bo Master permission not reproduced.

ZYNQ QSPI Controller Application Note