0X0000005C Blue screen Problem solving

When installing the operating system on a wave Inspur server, a 0x0000005c blue screen error appears, determined to be caused by x2apic, enter the BIOS's CPU setup option, set the X2APIC option to disable, reboot the machine, and complete the installation.
First explain the APIC (Advanced Program Interrupt Controller), and do not mix with ACPI (Advanced Configuration and Power Interface). The system can run in APIC mode. Enabling the APIC mode will extend the optional interrupt request IRQ system resource. Set values are: Enabled (open), Disabled (closed), according to IBM's instructions, open APIC mode can be the system default 15 IRQ (interrupt request) to share 22, can solve the problem of excessive equipment caused by interruption of conflict.
You can enable X2apic mode on a computer that is running Windows Server 2008 R2, and you can support more than 255 processors for your computer.
Quote http://blog.csdn.net/witsmakemen/article/details/18403391, make a note
The predecessor of APIC is pic, for example: 8259A.
2 Class APIC

1. Local APIC, direct Lian processor, each processor one. 2. I/O APIC, management peripherals over the interruption, usually a machine inside one (even multi-core system)
The INTEL IA32 Manual is about the local APIC, and the APIC below refers to the local APIC. The so-called local, is relatively processor, from the processor is relatively near, so called Local.

Local APIC can handle the following source of interrupts: 1 locally connected I/O devices. such as equipment directly attached to the foot of the lint0,lint1 tube.
2 external I/O devices. The interrupts generated by these devices are preceded by I/O APIC and then reached the processor via the local APIC.
3 interrupts between Inter-processor interrupts (IPIs) processors. Multiprocessor architectures are now common. When a processor wants to break another one, it can use IPI.
4) APIC Timer interrupt. The APIC has a timer on it, which is also very common in the OS.
5 Performance monitoring counter interrupts, performance monitoring counters are interrupted.
6) temperature sensor is interrupted. On the Pentium 4 and Xeon processors.
7) APIC INTERNAL error interrupt.


APIC can be viewed as a stand-alone piece of hardware that has its own stack of registers, called the local vector table or LVT. You can read and write to control some of the features and settings of APIC.


APIC can actually be subdivided into 3 versions:
1.APIC (early P6)
2.xAPIC (PENTIUM 4 and XEON)
3.x2apic


The APIC version can be detected with CPUID instructions.


In Xapic mode, registers are mapped to a physical address through memory. has a default value. To prevent conflicts with other addresses, this site can be assigned to another location. BIOS developers may use this feature when dealing with APIC.


In X2apic mode, the memory-mapped method is removed to read the APIC registers, but the MSR method is used. MSR's full write is the Model-specific register (each model-specific register) The advantage is that there is no need to worry about the conflict of memory address.


There are some rules between the opening, closing, and state switching of different APIC modes. If you want to change these places yourself, you need to follow the rules. Also note that in X2apic mode, when writing registers do not guarantee the order, so be careful with yourself, such as using a barrier or something.