0X0000005C Blue screen Problem solving

When installing the operating system on a wave Inspur server, a 0x0000005c blue screen error occurred, determined to be caused by x2apic, enter the BIOS CPU settings option, set the X2APIC option to disable, restart the machine, and complete the installation.
First to explain the next APIC (Advanced Program Interrupt Controller), do not mix with ACPI (INTERFACE), power management. The system can be run in APIC mode. Enabling APIC mode will extend the optional interrupt request IRQ system resource. Setting values are: Enabled (ON), Disabled (off), according to IBM's instructions, the open APIC mode can be the system default 15 IRQ (interrupt request) to share 22, can resolve the excessive device and cause the problem of interrupt conflict.
In a computer that is running Windows Server R2, you can enable X2apic mode, and the computer can support more than 255 processors.
Quote http://blog.csdn.net/witsmakemen/article/details/18403391, make a note.
The APIC is formerly known as PIC, for example: 8259A.
Class 2 APIC

1. LOCAL APIC, direct connect processor, each processor one. 2. I/O APIC, manage interrupts from peripherals, usually one inside a machine (even multicore systems)
The INTEL IA32 Manual is about the local APIC, and the APIC below refers to the local APIC. The so-called local, is relatively processor, from the processor relatively close, so called Local.

The local APIC can handle the following interrupt sources: 1) locally connected I/O devices. For example, a device that is directly attached to a lint0,lint1 pin.
2) external I/O devices. Interrupts generated by these devices go through the I/O APIC before reaching the processor via the local APIC.
3) interrupts between Inter-processor interrupts (IPIs) processors. Multiprocessor architectures are now common. When a processor wants to break another one, it can use the IPI.
4) The APIC timer is interrupted. The APIC has its own timer, which is also very common in the OS.
5) Performance monitoring counter interrupts, performance monitoring counter interrupted.
6) The temperature sensor is interrupted. Available on Pentium 4 and Xeon processors.
7) The APIC internal error is interrupted.


The APIC can be seen as a standalone piece of hardware with its own stack of registers called the local vector table or LVT. You can read and write to control certain features and settings of the APIC.


The APIC can actually be subdivided into 3 versions:
1.APIC (early P6)
2.xAPIC (PENTIUM 4 and XEON)
3.x2apic


Detecting the APIC version can be used with the CPUID instruction.


In Xapic mode, registers are mapped to a physical address through memory. has a default value. To prevent conflicts with other addresses, the base site can be re-assigned to another location. BIOS developers may use this feature when dealing with APIC.


In X2apic mode, the memory-mapped method is removed to read the APIC registers, but the MSR is used. The full write of the MSR is the Model-specific register (each model-specific register) and the benefit is that there is no need to worry about conflicting memory addresses.


There are a few rules between opening, closing, and state switching of different APIC modes. If you want to change these places yourself, you need to follow the rules. Also note that in X2apic mode, when writing registers do not guarantee the order, so be careful, such as with a barrier and so on.