Chapter 1.Introduction to Signal Integrity Analysis-Basic Definitions and Four Types of Noise Problems
First. Definition of high speed
When the clock frequency exceeds 100 MHz or the rising edge is less than 1 ns, the signal integrity effect becomes important. This situation is often referred to as the high-frequency domain or high-speed domain. These terms mean that in products or systems where the interconnect is no longer transparent to the signal, one or more signal integrity issues can occur if care is not taken.
Second.The scope of interconnection
Physical interconnections (interconnects) include intra-chip interconnects, chip packages, PCB boards, and electronic system connections, etc., which greatly affect the quality of signal and power distribution networks at high speeds.
Real interconnection lines, including in-chip wiring, pressure bonding points, package leads, chip pins; PCB board wire connectors, lines, connectors, connection cables, etc. outside the chip. In addition, there are various passive components, including dielectrics, substrates, shielding boxes, cases, racks, and so on.
Third. Definition of signal integrity (SI) and four types of signal integrity issues
• Signal Integrety (SI) The original meaning: whether the signal can maintain the waveform it should have.
• Signal integrity refers to all problems caused by interconnect lines in circuit design. It mainly studies how the electrical characteristics of interconnect lines and the voltage and current waveforms of digital signals affect the performance of the product.
• Main performance: influence on timing, signal ringing, signal reflection, near-end crosstalk, far-end crosstalk, switching noise, non-monotonicity, ground bounce, power bounce, attenuation, capacitive load, electromagnetic radiation, electromagnetic interference, etc.
• The root cause of the signal integrity problem is a reduction in signal rise time. Even if the wiring topology does not change, if an IC chip with a small signal rise time is used, the existing design may fail.
Broadly speaking, signal integrity refers to all problems caused by interconnect lines in high-speed products. It mainly studies how the electrical characteristics of the interconnects when they interact with the voltage and current waveforms of digital signals affect the performance of the product.
All these issues are divided into the following three effects and consequences:
Timing
Noise
3. Electromagnetic interference (EMI)
All effects related to signal integrity noise issues are related to one of four specific noise sources:
1. Signal integrity of a single network;
2. Crosstalk between two or more networks;
3. Rail collapse in power and ground distribution;
4. Electromagnetic interference and radiation from the entire system.
1.Signal integrity of a single network
When a signal is output from a drive source, the current and voltage that make up the signal treat the interconnect as an impedance network. As the signal travels along the network, it constantly feels the transient impedance change caused by the interconnect. If the perceived impedance of the signal remains the same, the signal remains undistorted. However, once the impedance changes, the signal is reflected at the change and distorted as it passes through the rest of the interconnect. If the impedance changes are large enough, distortion can cause false triggering.
Any feature that changes the cross-section or network geometry will change the impedance felt by the signal. All the characteristics that change the impedance are called mutations, and each mutation will cause the original pure shape of the signal to be distorted to some extent. The situation that changes the impedance felt by the signal comes from the following points:
>> Line width change;
>> layer conversion;
>> Return the gap on the plane of the path;
>> Connector;
>> Branch line, T-line or pile line;
>> The end of the network.
These impedance jumps are caused by cross sections, wiring topologies, or additional components. The most common mutations occur at the end of the line, usually with a high open input impedance of the receiver or a low output impedance of the driver.
The method to reduce the impedance mutation and ask Zhao is to keep the impedance felt by the signal in the whole network unchanged.
This method is generally implemented in three steps.
First, use a circuit board with constant or "controllable" line impedance, which usually means using uniform transmission lines.
Second, provide the wiring rules for the topology that keeps the impedance along the line constant.
Finally, place resistors in critical places to match them to control reflections and try to make the received signal cleaner.
Figure 1.5 shows the bad signal quality (ringing) caused by the sudden change of impedance in the same network and the signal quality (excellent) when using the termination resistor to control the sudden change of impedance.
It is generally believed that the "ringing phenomenon" is actually caused by reflections caused by sudden changes in impedance.
Figure 1.5
When unterminated, ringing occurs on the interconnect; when the source is terminated in series, the signal quality on the interconnect is excellent. In both cases, the PCB line is only 2 inches long. Each division on the vertical axis represents 1V, and each division on the horizontal axis represents 2ns.
The effect of any mutation on the signal is related to the rising edge of the signal. As the rising edge becomes shorter, the magnitude of the distortion increases. That is to say, in 33 MHz clock design, the mutation is not a problem, but it can become a problem in 100 MHz clock design.
The above is a sudden change caused by impedance mismatch. In addition, there are three aspects of signal quality problems:
There are two other aspects of signal quality in a single network. Due to the frequency-dependent losses of the conductor and the medium on the line, the high-frequency signal components are attenuated more than the low-frequency signal components. As a result, the rising edge of the signal becomes longer during propagation. When this rising edge is degraded to close to a 1-bit period, the digital information of the signal will be distorted, which is called inter-symbol interference (ISI). When the data transfer rate is equal to 1Gbps or higher, it will be the main cause of the problem.
The third aspect that affects signal quality in a single network is timing. The time delay difference between two or more signal paths is called skew. When there is an unexpected misalignment between the signal line and the clock line, false triggers and logic errors may occur. When there is a misalignment between the two lines of a differential pair, part of the differential signal will be converted into a common mode signal and the differential signal will be distorted. This may also cause ISI or false triggering.
A timing problem during misalignment is mostly caused by the electrical characteristics of the interconnect. The total length of the interconnect has the greatest effect on the misalignment. As long as the layout design is carefully matched to the length between the interconnects, the parity can be easily resolved. However, the delay is also related to the local dielectric constant felt by each signal, which is often difficult to solve.
2. Crosstalk
When the network propagates signals, some voltages and currents can be transferred to the adjacent static network, which is only engaged in its own affairs. Even if the signal quality on the first network (dynamic network) is very good, some signals are coupled to the second static network in the form of harmful noise.
Crosstalk occurs in two different situations: when the interconnect is a uniform transmission line (as most lines on a circuit board) and when the interconnect is a non-uniform transmission line (such as connectors and packaging). On a controlled impedance transmission line, the line has a wide uniform return path, and the relative capacitive coupling and inductive coupling are comparable in size. In this case, the two types of effects are not superimposed on the near and far ends of the static line (near-end crosstalk and far-end crosstalk).
When the return path is a uniform plane, it is the structure that achieves the lowest crosstalk. Once the uniform plane of the return path is changed, the coupling noise between the two transmission lines will increase. This usually happens (for example, when a signal passes through a connector and the return path common to multiple signals is a pin instead of a plane), inductively coupled noise increases more than capacitively coupled noise.
When inductive coupling noise is dominant, such crosstalk is generally classified as switching noise, AI noise, dl-dt noise, ground bounce, simultaneous switching noise (SSN), or simultaneous switching output (SSO) noise. This type of noise is caused by coupled inductance, the so-called mutual inductance. Most switching noise occurs at connectors, packages, and vias. In these structures, the conductor of the circuit's return path is not a large uniform plane. Later chapters in this book will explain that ground bounce is actually a special case where the return circuits on the same conductor overlap, and the mutual inductance between these paths is very large.
By understanding the nature of capacitive coupling and inductive coupling, you can optimize the physical design of adjacent signal lines and reduce coupling, which is usually as simple as separating the lines far. In addition, for wires with the same characteristic impedance, using a material with a smaller dielectric constant will reduce crosstalk. Certain aspects of crosstalk, especially switching noise, increase with increasing interconnect length and decreasing rising edges. The shorter the rising edge, the more severe the crosstalk generated by the signal. On the other hand, making the interconnects as short as possible, such as using the chip minimum size package (CSP) and high-density interconnects (HDI), can help reduce crosstalk.
3. Track collapse noise
The problem of noise is not only caused in the signal path, it is also a fatal problem in the power and ground distribution network (powering the chip). When the current through the power and ground paths changes, such as when the chip's output is flipped or the gate in the core is flipped, a voltage drop will be generated on the impedance between the power path and the ground path. This voltage drop means the voltage supplied to the chip Reduced, called the voltage drop or collapse between power and ground.
The trend in high-performance processors and some application specific integrated circuits is: low-voltage source power supply, high power consumption. The internal reason is that each gate consumes a certain amount of energy in each cycle, and the number of gates on the chip is increasing, and the switching speed is faster and faster. It is assumed that the same energy is consumed every cycle. The more frequently, the average power consumption becomes higher.
The combination of these factors means that there is a larger switching current in a shorter time, so that the amount of tolerable noise will be smaller. As the drive voltage decreases and the magnitude of the current increases, any voltage drop associated with track collapse will become an increasingly serious problem.
Tip The goal of designing power and ground distribution is to minimize the load resistance of power-distribution sysgem (PDS).
PDS is sometimes called power-distribution network (PDN).
Under the premise of low impedance of the power distribution system, even if there is current switching and switching in the PDS, the voltage drop across the lower impedance can be maintained at a tolerable level.
The following characteristics should be considered when designing a low impedance PDS:
>> The medium of the adjacent power and ground distribution plane should be as thin as possible to make them closer to each other;
>> Install multiple low inductance decoupling capacitors;
>> Arrange multiple short power and ground pins when packaging;
>> Add decoupling capacitors on-chip.
The use of an ultra-thin, plutonium-dielectric constant stack between the power and ground planes helps to minimize orbital collapse. For example, C-Ply from 3M Company, this material has a thickness of 8um and a dielectric constant of 20. When using this material to make the power and ground planes on special circuit boards, its ultra-low loop inductance and large distributed capacitance significantly reduce the power and ground distributed impedance.
4.Electromagnetic interference
The electromagnetic interference problem includes three aspects: noise source, radiation propagation path and antenna. The source of every signal integrity problem mentioned earlier is also the source of electromagnetic interference.
Most of the radiated voltage sources come from power and ground distribution networks. In general, a physical design that reduces orbital collapse noise also reduces radiation.
The shielding box greatly reduces the noise leaked to an antenna, and many poorly designed circuit boards can be compensated by a good shield.
In addition, if the cable has to extend to the outside of the shielding box, and the cable extends to the outside of the shielding box, it will act as an antenna and generate radiation. Ferrites can be used on cables to reduce antenna effects.
Fourthly. important inferences about signal integrity
1. As the rising edge decreases, the above 4 problems will become more serious
All the aforementioned signal integrity problems are measured by the rate of change of current or voltage, which usually refers to dI / dt or dV / dt. The shorter the rising edge, the larger the dI / dt or dV / dt. As the rising edge decreases, the noise problem inevitably increases, which is more difficult to solve.
2. Effective solutions to signal integrity are largely based on an understanding of interconnect impedance.
If you have a clear and intuitive understanding of impedance, and you can associate the physical design of the interconnect with the interconnect impedance, you can eliminate many signal integrity issues during the design process.
Fifthly. Trends in Electronics
Tips: As the feature size of transistors continues to shrink, the rising edge must continue to decrease, and the clock frequency must also continue to increase.
As the clock frequency increases, the rising edge of the signal will inevitably decrease. This is because reading the gate of the data line or clock line requires sufficient time to correctly read the signal to correctly determine whether the signal is at a high level or not. Low state.
This means that only a short time is left for signal conversion. Regardless of whether it is a rising edge or a falling edge, the measured conversion time is usually 10% to 90% of the final value, which is called the 10% to 90% rising edge. Figure 1.15 shows a typical clock waveform and assigned conversion time. In most high-speed digital systems, the rising edge of the distribution is approximately 10% of the clock period. Based on this inference, the relationship between the rising edge and the clock frequency is approximately:
Rising edge: The time it takes for the signal to rise from 10% Vpp to 90% Vpp, referred to as the "rising edge", and is denoted as Δt;
The first is defined as 10-90 rise time, that is, the time it takes for the signal to rise from 10% to 90% of the high level. The other is a rise time of 20-80,
That is, the time it takes for the signal to rise from 20% to 80% of the high level. Both are used, as can be seen from the IBIS model. For the same waveform,
Naturally the 20-80 rise time is shorter.
Among them, RT represents the rising edge (unit is ns), Fclock represents the clock frequency (unit is GHz).
Because all chip manufacturers have turned to lower cost and better production processes, the rising edge of the chips produced is shorter. Although the clock frequency is lower than 50MHz, signal integrity may still occur in the product. Sexual questions.
