Processor architecture
4.1 Y86 Instruction Set architecture
4.1.1 Programmer Visible State
Each instruction in the Y86 program reads or modifies portions of the processor state, called the programmer's visible state.
4.1.2 Y86 directive
4 Instructions: IRMOVL,RRMOVL,MRMOVL,RMMOVL, indicating the format of the source and destination, respectively
4 integer operation instruction: Addl,subl,andl,xorl
7 Jump Code Instruction JMP,JLE,JL,JNE,JGE,JG
6 Conditional Delivery Instructions CMOVLE,CMOVL,CMOVE,CMOVGE,CMOVG
The call command returns the address to the stack and then jumps to the destination site
PUSHL and POPL instructions are implemented into the stack and out of the stack
Execution of halt instruction stop instruction
4.1.3 Instruction Encoding
Instruction set important properties: Byte encoding must have a unique interpretation that is either a sequence of bytes or a code that is a unique sequence of instructions
The destination address of the branch instruction and the calling instruction is an absolute address
4.1.4 Y86 Anomalies
Value |
Name |
Meaning |
1 2 3 4 |
AOK HLK Adr Ins |
Normal operation Processor execution Halt instructions Illegal address encountered Encounter illegal instructions |
4.2 Logic Design and seal Control Language HCl
4.2.1 Logic Gate
And,or,not
&&,| |,!
4.2.2 Combination Circuit and HCl Boolean expression
By combining a lot of logic gates into a network, you can form a computational block called a combinational circuit.
Multiplexer: According to the value of the input control model, choose a different set of numerical signals
4.2.5 Memory and Clock
Clock registers
Random access memory
sequential implementation of 4.3 Y86
4.3.1 will process the organization into stages:
Take a finger
Decoding
Perform
Visit
Write back
Update pc
4.3.2 SEQ Hardware structure
Take a finger
Decoding
Perform
Visit
Write back
20135234 Ma Qiyang-—— Information Security system design basics Sixth Week study summary