20145235 "Information Security system design basics" No. 06 Week Study summary _02

20145235 "Fundamentals of Information Security system design" NO. 06 Week study summary _014.1.4 Y86 anomaly

Some values for the visible status Code stat:

1:AOK program performs normally

2:HLT indicates that the processor executed a halt instruction

3:adr means that the processor reads from an illegal memory address or writes to an illegal memory address.

4:ins indicates that an illegal instruction was encountered

4.1.5 Y86 Program

“.” The first word is the assembler command, which tells them that the assembler adjusts the command so that it can generate code or insert data

P239 Y86 Program Structure:

• Declaring the code to produce the starting address (. POS 0)
• Initializing stack pointers and frame pointers
• Open addresses for data declared by code
• Allocating space to stacks

Command simulator to become a yis.

The simulator prints only the words in the register or memory that were changed during the simulation. The left is the original value and the right is the final value.

4.1.6

For "PUSHL%esp" in the last semester's compilation, it is specified that the data is now push, then the pointer SP is modified, and for "Popl%esp", the pointer is modified before the pop. 4.1.6, however, is uncertain.

4.2 Logic Design and hardware control Language HCL

To achieve a digital system, three main components are required:

Calculates the logical structure of the bitwise operation, the memory element that stores the bits, and the clock signal that controls the update of the memory element.

4.2.1 Logic Gate

Logical Operations:&&, | |,!

Bitwise arithmetic:&, |, ~

4.2.2 Combination Circuit and HCl Boolean expression

By combining many logic gates into a single network, it is possible to build computations fast, called combinational circuits. Limitations: Outputs cannot be linked together, must be guaranteed without loops

4.2.3-character combination circuit and HCl integer expression

Having studied HDL in a sophomore, this verse has been mastered.

4.2.5 Memory and Clock

Storage devices are controlled by the same clock.

A clock register (a register) stores a single bit or word. The clock signal loads the input value.

Random access memory (memory) stores multiple words, using the address to select the read or which word to write.

In hardware, the register directly connects her input and output lines to other parts of the circuit. In machine-level programming, the register is one of the few addressable words in the CPU, where the address is the ID of the register.

Register: Enter x, current status, output.

Register File:

Read ports: Address inputs (SRCA and SRCB), data output (Vala and Valb)

Write Port: DSTW (Address input), VALW (data input)

Clock signal

The register file is not a composite circuit because it has an internal storage, which is a combined logical block with address input and data bit output.

Data memory: There is an address input, write data output, read the data output.

4.3 Y86 The order of implementation 4.3.1 will process the organization into stages

① (address is the value of the program counter PC)

Register read instruction Byte (4-bit instruction code Icode 4-bit function code ifun)

Register designator byte (indicates one or two register operator RA and RB)

Remove the four-byte constant (VALC)

Calculates the address of the next instruction valp=pc+ the number of bytes taken out of the instruction (not updated)

② decoding

Reads up to two operands from the register file, resulting in a value of Vala or Valb

③ execution

The arithmetic unit/logic unit (ALU) either executes the operation specified by the instruction, calculates the valid address of the memory reference, or increases or decreases the stack pointer. Get Vale.

Here you can set the condition code

④ visit

Data can be written to memory or read from memory. The value read is Valm.

⑤ Write back

The writeback stage can have up to two results into a register file.

⑥ Update pc

Pc=valp

When performing these stages of an audible abnormality, the processor stops: it executes a halt instruction or an illegal instruction, or reads or writes an illegal address. Then enter the exception handling mode, which executes the type of exception that is determined by the code.

OPl (four integer operations) are all made up of the same icode.

Feelings:

This week finally came into contact with the core of the computer (which can be said to be the kernel bar), and then suddenly took the knowledge learned from the top-down series together: from a C program code, to the assembly code, and then to the machine code, and finally to the computer processor how to execute, although the time to learn the assembly is very confusing, Through this week's learning, a framework of knowledge is framed in the mind. This week's content includes the Y86 instruction set, the HCL, and the Y86 sequence implementation. The first two are well mastered, Y86 and IA32 are almost as simple as IA32, and HCL is similar to a sophomore HDL, much simpler than HDL. The sequential implementation of Y86 is interesting because it is the kernel that touches the computer.

20145235 "Information Security system design basics" No. 06 Week Study summary _02