Sixth chapter memory Structure level
- The CPU executes instructions, while the memory system stores instructions and data for the CPU.
- The memory system is a linear byte array.
- In fact, a memory system is a hierarchical structure of storage devices with different capacity, cost, and access times. A hierarchical structure of storage devices that are near the small, cost, and access times of the CPU.
- Cache memory is the buffer area of data and instructions as primary memory.
- Main memory temporarily stores data stored on large, slow disks, which are often used as buffers of data stored on disks or tapes of other machines connected over the network.
- The basic properties of locality: Programs with good locality tend to access the same data set again and again, or tend to access neighboring collections of data. Programs with good locality tend to have more access to data from higher levels in the memory hierarchy than programs with poor locality, and therefore run faster.
6.1 Storage Technology 6.1.1 Random access storage
- Random access memory is divided into two categories: static and dynamic.
- SRAM is faster than DRAM, but much more expensive.
- SRAM is used as a cache memory, either on the CPU chip or under the chip.
- DRAM is used as a frame buffer for primary and graphical systems.
- SRAM and DRAM
- SRAM stores each bit in a bistable memory unit. It can save two different voltage configurations indefinitely.
- DRAM stores each bit as a charge to a capacitor.
- SRAM is strong anti-jamming, faster access than DRAM, more expensive, more power consumption.
- The traditional DRAM
- A DRAM chip is divided into a D-cell cut into R row C columns, each of which consists of a W DRAM unit. The DRAM chip is connected to the circuit of the storage controller, which can transmit the W bit to the chip or the W bit from the chip at one time.
- The circuit designer reduces the number of pins on the chip by causing the DRAM to be organized into two-dimensional arrays instead of linear arrays.
- The DRAM chip is packaged in a memory module and is plugged into the expansion slot on the motherboard. A single cell stores a single byte.
- Non-volatile memory
- If power is lost, SRAM and DRAM will lose their information.
- Prom can be programmed once
- Epromm 1000 Times
- EEPROM 10 5-Time Square
- Flash memory is a class of nonvolatile memory, based on EEPROM, the SSD is based on EEPROM.
- The program stored in the ROM device is called the firmware.
accessing main memory
- Bus things: Transfer from main memory to CPU is read transaction, from CPU to main memory called write transaction.
- A bus is a set of parallel conductors that can carry addresses, data, and control signals. Depending on the design of the bus, data and address signals can share the same set of conductors, or they can be used differently.
- The system bus connects the CPU and I/O bridge, and the memory bus connects the I/O bridge and main memory.
- Three steps to read a transaction:
- The CPU places address a on the system bus, and the I/O bridge transmits the signal to the memory bus. Second main memory senses the address signal on the memory bus, reads the address from the memory bus, extracts the data word from the DRAM, and writes the data to the memory bus.
- The I/O bridge translates the memory bus signal into a system bus signal and then travels along the system.
- Finally, the CPU senses the data on the system bus and copies the data to the appropriate registers.
- Three steps to write a transaction:
- The CPU places the address on the system bus, the memory reads the address from the storage bus, and waits for the data to arrive.
- The CPU copies the data word of the corresponding register to the system bus.
- Main memory reads the data word from the memory bus and stores the bits in DRAM.
6.1.2 Disk storage
- The disk is made up of one or more platters, which are encapsulated in a sealed package with two surfaces per platter, each with a set of concentric circles for the track, each of which is divided into a set of sectors, each of which contains an equal number of data bits.
- Disk capacity = number of sectors bytes * Sectors * Number of tracks * Number of surfaces * Number of discs
- Taccess=tavg seek +tavg rotation +tavg transfer
4. Connecting to I/O devices
- Peripheral devices are connected to the CPU and main memory via the I/O bus.
- A universal Serial Bus controller is a transit mechanism connected to a USB device. USB is a standard that is widely used.
- The graphics card (or adapter) is also connected to the I/O bus.
- The host bus adapter connects one or more disks to the I/O bus, using a communication protocol defined by a particular host bus interface.
Access Disk
- The CPU uses a technique called memory-mapped I/O to issue commands to I/O devices, where a block of address space is reserved for communication with I/O devices in a system that uses storage-mapped I/O. Each such address is called a port. When a device is connected to a bus, it is associated with one or more ports.
Disk Read
- The first instruction is to send a command word that tells the disk to initiate a read and also sends other parameters.
- The second instruction should read the logical block number.
- The third instruction indicates the main memory address where the contents of the disk sector should be stored.
- The logical block number translates a sector address and then transfers the content to main memory without CPU interference, a process known as direct memory access. This data transfer is called DMA transfer.
- When the volume of a disk sector is securely stored in main memory, the disk controller notifies the CPU by sending an interrupt signal to the CPU.
Problem:
may be a bit low-level, the book says that the main memory of the disk data transfer, do not need CPU interference, then this is not a bug, can be free to write memory by the disk data? If there is no bug, how can it be ensured that data transferred from disk to main memory is legitimate?
20145235 "Information Security system design basics" No. 07 Week study summary _1
