1. Transfer Control--
Call command: The address of the instruction that is followed by the beginning of the called procedure. The effect is to put the return address into the stack and jump to the beginning of the called procedure.
RET instruction: POPs the address from the stack and jumps to this position.
Exercises :
Find out where the following code is wrong?
Movb $0xf, (%BL)---the destination operand can only be a register or a memory address. (%BL) Represents a value
MOVW (%eax), 4 (%ESP)---purpose operand and source operand cannot all be memory
Movb%si, 8 (%EBP)---instruction suffix does not match the register address
int arith(int x,int y,int z) { int t1 = x^y;
int t2 = 3*t1;
int t3 = ~t2;
int t4 = t3-z; return t4;
The following code snippet often appears in the compiled version of the library function:
Call Next
Next
POPL%eax
A. What value is the register%eax set to?
%eax is set to POPL address.
B. Explain why this call does not match the RET directive
This is not a real procedure call, because it is done in the same order as the instruction, and the return value is popped from the stack.
C. What is the function of this piece of code?
This is the only way to put the value in the program counter into an integer counter in IA32.
SEQ Hardware structure
- In SEQ, the processing of all hardware units is done in one clock cycle.
- Drawing conventions for SEQ Route diagrams:
- Light gray box indicates hardware unit
- The control logic block is represented by a gray rounded rectangle.
- The name of the line is indicated in the white ellipse.
- A data connection with a width of length is expressed as a line of medium roughness
- Data connections with a width of bytes or narrower are represented by a thin line
- The connection of a single bit is indicated by a dashed line
Timing of SEQ
- The SEQ implementation consists of a combination of logic and two types of memory devices:
- Clock Register program counter and Condition code register
- Random access memory register file, instruction memory, and data memory
- Each clock cycle, the program counter will be installed in the new instruction address, only when the integer operation instruction is executed, the condition code register will be loaded, only when the RMMOVL, PUSHL or call instructions are executed, the data memory is written, and the two write ports of the register file allow two program registers to be updated per clock cycle.
- Organization calculation principle: The processor never needs to read the state updated by the instruction in order to complete the execution of an instruction .
- Clocks are used to control the updating of State elements, and values are propagated by combining logic.
Implementation of the SEQ phase
- refers to a stage where
- reads 6 bytes at a time with the address of the first byte of the PC.
-
icode : Control logical block calculation instructions
-
ifun : function code
- Three one-bit signal (calculated based on Icode value):
Instr_va Lid : illegal instruction found; need_regids : contains register designator byte; need_valc : include constant numbers
- The latter five bytes are the combined encoding of the Register designator byte and the constant number.
- decoding and writeback stages:
- All need to access the register file, according to the case of four ports, determine which register should be read to generate the signal Vala, Valb. The
- register file, which supports simultaneous two reads and two writes, each port has an address connection (register ID) and a data connection (32 lines), which can be used as the output word of the register file or as his input word.
- execution phase:
- includes arithmetic/logic unit (ALU), output is Vale signal. The ALU is typically used as a adder using
- including the condition code register
- to produce each run: 0, sign, overflow, generate signal set_cc
- access stage
- read or write program data 。 The
- two data blocks generate the memory address and the value of the memory input evidence, and two generate control signals indicating whether to read or write. When the read operation is performed, the data memory generates VALM.
- calculates the status code stat from the result of the instruction execution, based on Icode,imem_error,instr_valid,dmem_error.
- update pc stage
- generates a new value for the program counter, depending on the type of instruction and whether to select the branch, the new PC may be valc, Valm, or Valp.
Please explain why there is only one if statement in the C language code, and the assembly code contains two conditional branches?
A: The first conditional branch is part of the && expression implementation. If the test fails for a non-empty p, the code skips the test of a>0.
Installation of the Y86 simulator
- You can refer to this post: (http://www.cnblogs.com/hrhguanli/p/4594724.html),
20145309 Information Security system Design Fundamentals 7th Week study Summary
