20145311 "Information Security system Design Fundamentals" The sixth Week study summary textbook Learning content Summary
The tables in the book are still very important.
A program is compiled to run on one machine and cannot be run on another machine
Register%ESP are stack pointers, stack, call, and return instructions
Program Counter PC holds the address of the currently executing instruction
The three-bit condition: ZF, SF, and about holds information about the effects of recent arithmetic or logical operations
Y86 instruction set: The first byte of each instruction indicates the type of instruction, the high 4 bits is the code part, and the low 4 bits is the functional part
An important property of the instruction set is that the byte encoding must have a unique interpretation
IA32 (complex instruction set computer CISC) compact instruction set computer (RISC) Y86 instruction set with both properties
ARM instruction sets are widely used in embedded systems (e.g. mobile phones)
PUSHL%ESP instruction is pressed into the old value of the%ESP register
Implement three main components of a digital system: compute the combined logic of functions for bitwise operations, memory elements that store bits, control memory elements, updated clock signals
Clock register: Store single bit or word, clock signal control register load input value
Random access Memory: Store multiple words, use the address to choose which word to read or write
In machine-level programming, registers represent one of the few addressable words in the CPU
The order of the Y86 is implemented:
Fetch (the address of the next instruction of the current instruction Valp)
Decoding (reads up to two operands from the register)
Execute, visit, write back, update pc
The processor enters exception handling mode and starts executing special code that is determined by the type of the exception
One way to reduce complexity when designing hardware is to have different instructions share as much hardware as possible
The implementation of SEQ consists of combinational logic and two memory devices: Clock register (program counter and Condition Code register), random access memory
Important principle: The processor never needs to read the state updated by the instruction in order to complete the execution of an instruction
The only problem with SEQ is that it is too slow and the clock must be very slow so that the signal can propagate all phases in one cycle.
Y86 exception
Status code: Describes the overall state of the program execution.
值 名字 含义1 AOK 正常操作2 HLT 处理器执行halt指令(指令停止)3 ADR 遇到非法地址4 INS 遇到非法指令
In Y86, any code other than AOK causes the processor to stop executing instructions without an exception handler.
In the HCL, all word-level signals are declared as int, and the size of the word is not specified
Problems in teaching materials learning and the solving process
Follow those steps to configure it, basically.
. Ys is the source code. Yo is the result of the compilation and can be compiled with make instructions
Here are the two compiled Y86 instructions and the corresponding machine code: (to understand the meaning or read it)
The problem and the process of the work after class
HCl language doesn't really understand
This week's code hosting
Looks like there's no code
Other (sentiment, thinking, etc., optional)
This week's study is mainly about how the processor executes the program, the assembly language into the machine code after the implementation of the machine code, the books on the table is good-looking, combined with a few examples to understand the basic understanding, learning the Y86 instruction set architecture, At the same time to learn some of the previous semester HDL (Hardware description language) similar to some combination of circuit, gate circuit, timing circuit, and finally understand the HCL language, the feeling of the language is not fully understood, but also need to be further combined with examples to understand.
Learning progress Bar
|
lines of code (new | /Cumulative)
Blog volume ( | new/cumulative)
Learning time (new/cumulative) |
Important growth |
Goal |
5000 rows |
30 Articles |
400 hours |
|
First week |
100/100 |
1/2 |
10/10 |
|
Second week |
150/200 |
2/4 |
8/18 |
|
Third week |
200/250 |
1/5 |
5/23 |
|
Week Five |
50/300 |
1/6 |
9/32 |
Week Six |
20/320 |
1/7 |
8/40 |
Resources
- "In-depth understanding of computer system V2" Learning Guide
- ...
20145311 "Information Security system design Fundamentals" Sixth Week study summary