20145336 Zhang Ziyang "Information Security system design basics" 6th Week study Summary

Summary of learning contents of textbook

Learning Goals

1. Understanding the role of ISA abstraction
2. Master Isa, and be able to learn other architecture extrapolate
3. Understanding the pipeline and how it is implemented

Instruction Collective System: byte-level encoding of instructions and instructions supported by a processor, each of which has its own different Isa

Y86 Instruction Set architecture

Define an instruction set architecture that includes defining various state elements, instruction sets and their encodings, a set of program specifications, and exception handling.

• RF Program Register:%EAX,%ECX,%EDX,%EBX,%ESI,%EDI,%ESP,%EBP (%esp to Stack, stack, call and return instruction as a stack pointer)
• PC Program Counter: Stores the address of the currently executing instruction
• Deme Memory: A large byte array that holds programs and data
• Stat Program Status: Indicates the overall state of program execution
• CC Condition code: ZF, SF, of

Y86 directive

                                                                    Byte Halt 0|0                1nop 1|0 1RRMOVL RA,RB 2|0 |ra|rb 2irmovl V, RB 3|0 | F |rb| V 6rmmovl ra,d (rB) 4|0 |ra|rb| D 6MRMOVL D (RB), RA 5|0 |ra|rb| D 6OPL RA,RB 6|FN|RA|RB 2 JXX Dest 7|fn|                    Dest 5cmovXX ra,rb 2|fn|ra|rb 2call Dest 8|0 |                    Dest 5ret 9|0 1PUSHL RA A|0 |ra| F 2popl RA b|0 |ra|      F                             2 

• MOVL: first two letters specify source and destination format, immediate number (i), register (R), memory (m)
• Does not allow direct transfer from one register address to another memory address, nor does it allow the transfer of immediate numbers to memory
• OPL is a 4 integer operation instruction: Addl,subl,andl,xorl. Operation only on register data.
• JXX is a 7 jump instruction Jmp,jle,jl,je,jne,jge and JG. Depending on the type of branch instruction and the conditional Code selection branch.
• CMOVXX has 6 conditional directives: CMOVLE,CMOVL.CMOVE,CMOVNE,CMOVGE,CMOVG. These instruction formats are the same as RRMOVL, but the value of the destination register is updated only if the condition satisfies the required constraints
• Call returns the address to the stack, and then jumps to the destination address.
• The RET instruction returns from such a procedure call
• PUSHL and POPL implemented into stacks and stacks
• Halt stopped the execution of the instruction.

Instruction encoding

Read the instruction code look at each instruction the first byte indicates the type of instruction, the high four bits is the code part, the lower four bits is the function part.

There may be additional register designator bytes, which are set to RA,RB.

Some instructions need to append a four-byte constant number, as with IA32, and all integers are encoded with a small-end method

Any sequence of bytes is either a unique instruction encoding, or it is not a valid sequence

The first byte has a unique combination of code and functionality, so we can determine the length and meaning of the other hairpin bytes.

Y86 exception

值       名字                  含义1       AOK                 正常操作2       HLT                 处理器执行halt指令3       ADR                 遇到非法地址4       INS                 遇到非法指令

The ADR indicates that the processor attempted to read from an illegal memory address or to an illegal memory address

The processor typically calls an exception handler, which is pinned to handle an exception that encounters some type of

Logic design and hardware control Language HCL

A digital system requires three parts: the combined logic of the function that computes the bitwise operation, the memory element that stores the bits, and the clock signal that controls the update of the memory element.

Logic gates

Logic gates produce a Boolean function whose output equals their input bit value.

HCL expressions and && OR | | Not!!

Combinational circuits: Many logic gates are combined into a single net, which can constitute a block of computation, constructing two restrictions on these nets by 1. The outputs of two or more logic gates cannot be connected together 2. This web must be a ring-free.

The difference between the C language logic expression and the HCL logical expression 1. HCL output will continue to affect the outputs, the input changes, after a certain delay, the output will also change. C is evaluated only when it is encountered during program execution. 2. The logical expression of C allows the argument to be any integer, 0FALSE, and the other value represents true. Logical values operate on 0 and 1 only

Memory and Clock

• In order to produce a sequential circuit, a bitwise storage device must be introduced, and the storage device is controlled by the same clock signal.
• Clock Register: Stores a single bit or word, and the clock signal control register loads input values.
• Random access Memory: Store multiple words, using the address to choose which word should be read and written.
• The register is stable first (the output equals the current state), and the clock rising edge comes when the input signal is loaded.
• The register file has two read ports (A and B), a write port (W), allowing simultaneous multi-port read and write operations.

Y86 Sequential Implementation

The organizational phase will be processed

• Value: The value phase reads the instruction bytes from the memory, the value of the Address Commission counter, and the two thought parts of the instruction designator byte from the instruction, called Icode (instruction Code) and Ifun (instruction function). VAIP (the address of the next instruction) equals the value of the PC plus the length of the removed instruction.
• Decoding: Reads a maximum of two operands from the register file, obtaining Vala and/or VALB.
• Execution: The arithmetic logic unit (ALU) executes the operation specified by the instruction (according to the value of Ifun), calculates the valid address of the memory reference, or increases or decreases the stack pointer. The resulting value is called Vale. The condition code may also be set.
• Access: Writes data to memory, or reads data from memory. The value read is Valm.
• Write back: Up to two results can be written to the register file.
• Update PC: Sets the PC to the address of the next instruction.

Y86 instruction Set Calculation principle: The processor never needs to read the state updated by the instruction in order to complete the execution of an instruction.

implementation of the SEQ phase -The value phase includes the instruction memory hardware unit. -Decoding and writing stages: The register file has four ports. It supports simultaneous two reads (A and B) and two writes (E and M). Each port has an address link and a data link, the address understanding is a register ID, and the data connection is a set of 32 lines, either as a register file output word (for the read port), or as its input word (for the write port)-The memory stage: Read or write program data, Two control blocks produce values for memory address and memory input data. The other two blocks generate a control signal indicating whether read or write operations should be performed. When the read operation is performed, the data memory generates VALM. -Update PC Stage: Generates new values for the program counter, depending on the type of instruction and whether to select branches, the new PC may be valc, Valm, or Valp.

Problems in teaching materials learning and the solving process

In the Thursday blog, the teacher said to install Y86 Simulator hands-on practice, so I refer to the classmate's blog installed Y86, which is my installation after the completion of Y86 in the pipe folder input./PSIM-T-G. /y86-code/asum.yo

Enter Y86-code, Generate Asuml.yo

I try to knock the code out of the book, and then enter the following command

make clean

make 251pp.yo

You can then view the

　　

Code Managed Links: http://git.oschina.net/Zziyang/CS04

Learning progress Bar /Cumulative) new/cumulative)

	lines of code (new	Blog volume (	Learning time (new/cumulative)	Important growth
Goal	5000 rows	30 Articles	400 hours
Second week	0/0	1/2	19/20
Third week	80/80	1/3	25/44
Week Four	110/190	1/4	23/67
Week Five	60/250	2/6	26/93
Week Six	80/330	2/8	25/118

Resources

• "In-depth understanding of computer system V2" Learning Guide
• ...

20145336 Zhang Ziyang "Information Security system design basics" 6th Week study Summary