20145339 "Information Security system Design Fundamentals" 6th Week Study Summary

Processor Architecture Learning Goals

Understanding the role of ISA abstraction

Master Isa, and be able to learn other architecture extrapolate

Understanding the pipeline and how it is implemented

Isa:

The byte-level encoding of instructions and instructions supported by a processor is called his instruction set architecture (Instruction-set Architecture, ISA)

ISA provides a conceptual abstraction layer between compiler writers and processor designers, and compiler writers only need to know which instructions are allowed and how they are compiled. Modern processors may work in a very different way than the computational model implied by ISA. The ISA model should appear to be sequential instruction execution, however, the performance of the processor can be improved by simultaneously processing the different parts of multiple instructions at the same time as executing only one instruction. HCL: Hardware Control Language 4.1 Y86 instruction set architecture 1, Y86 instruction set:

More details on the Y86 directive:

IA32 's MOVL instruction is divided into 4 different instructions: the memory reference in the two memory transfer instructions of IRMOVL, RRMOVL, MRMOVL, and RMMOVL is the simplest form of base address and offset. In address calculation, we do not support the scaling of the second variable address register and any register values. As with IA32, no direct transfer from one memory address to another is allowed. In addition, the immediate number is not allowed to be transferred to the storage.

There are 4 integer operation instructions: Addl, Subl, Andl, Xorl.

6 Conditional Delivery Instructions: Cmovle, CMOVL, Cmove, Cmovne, Cmovge, CMOVG.

7 Jump commands: jmp, Jle, JL, je, jne, Jge, and JG call instructions will return the address to the stack and then jump to the destination address. The RET instruction returns the execution of the halt instruction stop instruction from such a procedure call. There is an equivalent hlt in the IA32.

2. Instruction code:

The first byte of each instruction represents the type of the instruction. This byte is divided into two parts, each part 4 bits. The high 4 bits are part of the code, and the 4th bit is the feature section.

function values are only useful if a single set of related directives is shared with one code.

function code for the Y86 instruction set:

All integers are encoded using a small-end method. These bytes appear in reverse order when the instruction is written in the disassembly format.

An important property of the instruction set is that the byte encoding must have a unique interpretation.

3, Y86 exception:

In a more complete design, the processor will often invoke an exception handler, which is specified to handle some type of exception encountered. Exception handlers can be configured with different results.

The only tool to create Y86 is the assembler.

YIS (instruction Set simulator), which is designed to simulate the execution of Y86 machine code programs without attempting to emulate the behavior of any specific processor implementation.

4. Details of the Y86 directive

The PUSHL instruction will reduce the stack pointer by 4 and write a register value to the memory. Therefore, the behavior of the processor is not deterministic when executing the PUSHL, because the registers to be placed on the stack are modified by the same instruction. There are usually two kinds of conventions:

The original value of the pressed-in%ESP is pressed into the value of the%esp minus 4.

4.2 Logic Design and hardware control language HCL1, logic gates

A logic gate is a basic computational element of a digital circuit. They produce output that is equal to some boolean function of their input bit value.

and && OR | | Not!

The logic gate symbol differs from the C language symbol because the logical gate operates on only the number of individual bits, not the entire word.

The logic gate is always active. Once the input of a door changes, in a very short period of time, the output will change accordingly.

By combining a lot of logic gates into a single network, we can construct a computational block called a combinational circuit. There are two limitations to building these nets:

The outputs of two or more logic gates cannot be connected together, otherwise they may cause conflicting signals on the line and may lead to the next illegal voltage or circuit failure. This net must be non-ring. That is, it cannot form a circuit.

The difference between an HCL expression and an expression in the C language:

Because the combinational circuit is composed of a series of logic gates, its properties are the output will continue to respond to input changes, if the input of the circuit changes, after a certain delay, the output will change accordingly. In contrast, C-expressions are evaluated only when they are encountered during program execution. The logical expression of C allows the argument to be any integer, 0 for false, and any other value to represent true. And the logic gate is only 0, 1. The logical expression of C has a property that they may only be partially evaluated. If an and or or operation result is determined only by evaluating the first parameter, you do not need to apply for the second parameter. The logic gate simply responds to the change of the input, while the combinatorial logic has no partial evaluation of the rule.

2, word-level combination circuit and HCL integer expression

The combination circuit that performs the word-level computation calculates each bit of the output word with a logic gate based on the individual bits of the input word.

In the HCL, we declare all word-level signals as int, without specifying the size of the word

In the HCL, a multiplexed function is described using a condition expression. Each case I has a Boolean expression select and an integer expression, expr. The former indicates when to choose this case, the latter represents the resulting value

The Arithmetic/logic unit (ALU) is a very important combination circuit. This circuit has 3 inputs: two data inputs labeled A and B, and a control input.

3. Memory and Cycle:

Clock Register: the abbreviation register. Stores a single bit or word. Clock signal control register load input value

Random Access Memory: abbreviated memory. Store multiple words, using the address to select the read or which word to write.

The register file has two read ports (A and B) and a write port W. Such a multi-port random access memory allows multiple read and write operations to be performed simultaneously. Each port has an address input indicating which program register to select.

20145339 "Information Security system Design Fundamentals" 6th Week Study Summary