2018-2019-1 20165210 "Information Security system Design Fundamentals" 4th Week Study Summary

2018-2019-1 20165210 "Information Security system Design Fundamentals" 4th Week study summary Textbook Learning content Summary ISA

• Concept:

The byte-level encoding of a processor-supported instruction and instruction is called its instruction set architecture Isa.

While the processor performance and complexity of each manufacturer is increasing, the different models remain compatible at the ISA level. Therefore, ISA provides a conceptual abstraction layer between the compiler writer and the processor designer.

The concept abstraction layer is the ISA model: The CPU allows instruction set encoding, and executes the instruction sequentially, i.e. take out an instruction first, wait until she finishes, and then start the next one. However, modern processors may actually work in a very different way than the computational model implied by ISA. By simultaneously processing different parts of multiple instructions, the processor can achieve high performance. However, it must demonstrate that it conforms to the ISA model's execution results.

In computer science, the idea is well known (abstract) to improve performance while maintaining a simpler, more abstract model.

• Instruction set:

An ISA may contain multiple instruction sets

The extended instruction set of the CPU is often referred to as the "instruction set of the CPU" (because the basic, quasi-decrement instructions appear to be commands that must be supported by the CPU). Each CPU is designed with a series of instruction sets that match its hardware circuitry.

80x86 command System, command by function can be divided into the following seven parts.

(1) Data transfer instructions.
　　

(2) arithmetic operation instruction.
　　

(3) logic operation instruction.
　　

(4) Serial operation instructions.
　　

(5) Control transfer instructions.
　　

(6) Processor control instructions.
　　

(7) Protection mode directive.

The core of the x86 instruction code is: Opcode, MODRM, and SIB. The Opcode provides the opcode of the instruction, MODRM and SIB provide the addressing mode of the operand.

RISC (thin instruction set computer) and CISC (complex instruction set computer) are two architectures of the current CPU. They differ in the different CPU design concepts and methods.

The early CPUs were all CISC architectures designed to perform the required computational tasks with minimal machine language instructions. For multiplication, for example, you might need an instruction on the CPU of the CISC architecture: MUL Addra, ADDRB can multiply the numbers in Addra and ADDRB and store the results in Addra. The Addra, the data in the ADDRB read into the register, and the operation to write the results back to memory all depend on the logic of the CPU design. This architecture increases the complexity of the CPU structure and the requirements for the CPU process, but is advantageous for the development of compilers. For example, the a*=b in the C program can be compiled directly into a multiplication instruction. Today only Intel and its compatible CPUs are using the CISC architecture.

The RISC architecture requires software to specify the individual steps of the operation. The above example if the implementation of the RISC architecture, will be Addra, ADDRB data in the register, multiply and write the results back to the memory of the operation must be implemented by the software, such as: MOV A, Addra; MOV B, ADDRB; MUL A, B; STR Addra, A. This architecture reduces CPU complexity and allows for more powerful CPUs to be produced at the same process level, but with higher requirements for compiler design.

Y86:

• Halt
  This command will terminate the execution of the instruction.

• Nop
  This is a placeholder instruction, he does not do anything, follow up in order to achieve the pipeline, it has a certain role.

• Xxmovl
  This is a series of data transfer instructions where r represents a register, m represents memory, and I represents an immediate number. For example, the RRMOV directive assigns the value of a register to another register.

• Opl
  Operation instructions, such as addition, subtraction and so on.

• Jxx
  Conditional jump instruction, according to the following conditions to jump.

• Cmovxx
  The conditional delivery instruction, followed by XX, represents the condition. In particular, conditional delivery occurs only between two registers and does not transfer data to storage.

• Call and RET
  The call and return instructions for the method. One will return the address into the stack and jump to the destination address. One will return the address into the PC and jump to the return address.

• Push and pop
  In-stack and out-of-stack operations

• Y86 exception
  For Y86, there is a stat status code in the visible state of the programmer, which marks the state of the program execution. Y86 needs to be able to do some processing according to Stat. Capture for simplicity, the execution of the instruction is stopped in addition to normal execution. In reality, there will be special exception handlers.

Y86 has four different status codes: AOK (normal), HTL (Execution halt instruction), ADR (illegal address), and ins (illegal instructions).

Problems in teaching materials learning and the solving process

(a template: I read this paragraph of text (quoted text), there is this problem (ask questions). I checked the information, there are these statements (quote), according to my practice, I get these experiences (describe my experience). But I still do not understand, my confusion is (explain confusion). "or" I oppose the author's point of view (presenting the author's point of view, his own point of view, and the reason). ）

• The difference between the problem 1:y86 and X86
• Problem 1 Solution:

Sometimes Y86 need two instructions to achieve the purpose of X86 an instruction can be achieved. For example, addl$4,%ecx in the X86 directive, because the ADDL instruction in the Y86 does not contain an immediate number, Y86 need to first deposit the immediate number as a register, that is, using the IRMOVL instruction, and then use ADDL to handle the addition operation

Other (sentiment, thinking, etc., optional)

86 is a reduced version of X86, whose goal is to implement a processor with a simple structure that helps us understand the design and implementation of the processor.

Last week's class lesson wrong question

2018-2019-1 20165210 "Information Security system Design Fundamentals" 4th Week Study Summary