2018-2019-1 20165329 "Information Security system Design Fundamentals" 4th Week Study Summary

2018-2019-1 20165329 "Information Security system Design Fundamentals" 4th Week Study Summary

Summary of learning contents of textbook

• Y86-64 directive: The y86-64 instruction is a subset of the x86-84 instruction set. It includes only 8-byte integer operations. There are 4 integer operations directives: ADDQ, SUBQ, ANDQ, and Xorq. There are 7 jump commands: jmp, Jle, JL, je, jne, Jge, and JG. There are 6 conditional delivery directives: Cmovle, CMOVL, Cmove, Cmovne, Cmovge, and CMOVG.

• The processor execution instruction encodes the instruction into a binary instruction conversion mode:

  Determine the instruction length, divide the sequence, and determine the specific instruction;

  Register indicator byte determines register, determines address and other information;

  The logic gate is the computing element of the computer, and the composition circuit is calculated.

  Each instruction requires several bytes, and the first byte of each instruction indicates the type of instruction: The high 4 bits are the code portion, and the lower 4 bits are the functional ones;

• Programmer-Visible state: Each instruction in the Y86-64 program reads or modifies portions of the processor state, which is known as the programmer's visible state. Includes: program register, condition code, program status, program counter, and memory.
• Y86-64 Status Code:
  Code value 1, named AOK, indicating normal operation;
  The code value 2, named Hlt, indicates that the halt command is executed by the encountering device;
  Code value 3, named ADR, indicates that an illegal address was encountered;
  Code value 4, named Ins, indicates that an illegal instruction was encountered.
• function code for the y86-64 instruction set:

• Y86-64 Program Register Identifier:

• Logic gate: The logic gate is the basic calculating unit of the digital circuit. They produce output that is equal to some boolean function of their input bit value. Include: with (and), or (or), and non (not). Combinational circuits: The combination of a lot of logic gates into a network, you can build a computational block. Combinational Circuits and HCl Boolean expressions

• Word-level combinational circuits and HCl integer expressions the computations required to implement all y86-64 directives can be organized into 6 basic stages. Include: Refer to, decode, execute, visit, write turn update pc.

• Fetch refers to: The reference phase reads the instruction bytes from memory, and the address is the value of the program counter.

• Decoding: The decoding phase reads a maximum of two operands from the register file, obtains the corresponding value, and reads the register specified in the instruction.

• Execution: The ALU either executes the operation specified by the instruction, computes the valid address of the memory reference, or increases or decreases the stack pointer.

• Visit: The data can be written to memory or read from memory.

• Writeback: Write-back Stage can write up to two results to the register file.

• Update PC: Sets the PC to the address of the next instruction.

• Seq Timing:
  The SEQ implementation consists of a combination of logic and two types of memory devices: clock registers and random access memory.

• Organization calculation principle: never read back. The processor never needs to read the state updated by the instruction in order to complete the execution of an instruction.

2018-2019-1 20165329 "Information Security system Design Fundamentals" 4th Week Study Summary