(5) 10 bit address of I2C bus and general broadcast address

In fact, I have never used a 10-bit address or a universal broadcast address. the general broadcast address should be used for communications between multiple MCU using I2C. although it is useless, it is still translated and may be used in the future:

10bit address: the number of addresses that can be extended by 10bit addressing. devices with 7bit and 10bit addresses can connect to the same I2C bus, and both 7bit and 10bit addressing can be used in all bus speed modes. however, 10bit addressing is rarely used. the 10bit slave address consists of two bytes after the start condition (s) or repeated start condition (SR. the first 7 bits of the first byte are 1111 0xx, and XX is the first two bits of the highest valid bits of the 10bit address. the 8bit of the first byte is the read/write bit, which determines the transmission direction. although 1111 XXX has eight possible combinations, only 1111 0xx can be used for 10bit addressing. the remaining 1111 1xx types will be used for future I2C extensions. the read/write formats described earlier for 7-bit addressing apply to 10-bit addressing. details: 1. the transmission direction from the master-transmitter to the receiver (10bit from the machine address) is not changed. after receiving the 10bit address after the start condition, the slave machine compares the first byte (1111 0xx) of the slave address with its own address and checks the eighth bit (read/write bit) whether it is 0. multiple devices may match and generate a response (A1 ). next, all the slave machines match their own address with the 8 bits (xxxx) of the second byte, then only one slave machine matches and generates a response (A2 ). the host address matches the status from the opportunity to the address until it receives the termination condition or repeats the start condition, followed by a different slave address. 2. the data received by the master-receiver from the transmitter (10bit from the address) changes the transmission direction after the second read/write bit. before the second response A2, the processing process is consistent with the master-transmitter addressing slave-receiver above. after repeated start conditions (SR), the matched State remains addressable from the opportunity. check whether the first 7bit of the first byte after the SR is correct, and then test whether the 8bit is 1 (read ). if this matches, the slave determines that it is addressed as a sender and generates a response A3. the slave-transmitter will remain addressable and knows the receiving termination conditions (P) or repeat the start condition (SR) with a different slave address. at this time, all the addresses from the opportunity to compare them with 11110xx and test the eighth (read/write bit ). however, they are not addressable, because the read/write bit is 1 for 10 bit devices, or the slave address of 1111 0xx does not match for 7 bit devices.
The following table describes the reserved addresses: [1] The general broadcast address is used to include software reset functions [2] No device can answer the start byte [3] The cbus address is retained, this allows devices compatible with the cbus bus and I2C bus in the same system. i2C compatible devices are not allowed to respond to this address [4] reserved for different bus formats
The universal broadcast address is used to simultaneously address all devices connected to the I2C bus. if a device does not need data when broadcasting an address, it can ignore it without generating a response. if a device requests data from a universal broadcast address, it can respond and act as a slave-receiver. when one or more devices respond, the host does not know how many devices have responded. each slave-receiver that can process this data can respond to the second byte. if the slave does not process these bytes, it can respond to Na. if one or more slave servers respond, the host cannot see Na. the meaning of a universal broadcast address is generally specified in the second byte. there are two situations to consider: 1. the minimum valid bits B is 0 2. the minimum valid bits B is 1 when B is 0, the second byte has the following definition: 1.0000 0110 (06 h): reset and write the programmable part of the slave address through hardware. when such two bytes are received, all devices that can respond to the broadcast address will reset and enter the programmable part of the address. preventive actions should be taken to ensure that the device does not bring SDA or SCL down after the power supply voltage is added, because these low levels will block the bus. 2.0000 0100 (04 H): programmable part of the slave address written by hardware. the behavior is the same as above, but the device does not reset 3.0000 0000 (00 h): this should not be used as the second byte to use the programming process sequence reference The Datasheet of the corresponding device

The software reset sends 0000 0000 (06 h) as the second byte after the universal broadcast (0000 0010) will cause the software reset. this feature is optional. Not all devices will respond to this command. when such two bytes are received, all devices that can respond to the broadcast address will reset and enter the programmable part of the address. preventive actions should be taken to ensure that the device does not bring SDA or SCL down after the power supply voltage is added, because these low levels will block the bus.
The START byte microcontroller can be connected to the I2C bus in two ways. A Microcontroller with on-chip hardware I2C bus interfaces can be used to receive only bus interruption requests. when a device does not have such an interface, it must use software to detect the bus. obviously, the more time the microcontroller detects or polls the bus, the less time it takes to implement its own functions. therefore, there is a difference in speed between fast hardware devices and the relatively slow microcontroller dependent on software polling. in this case, there is a starting process that is much longer than the normal time before data transmission. the starting process consists of the following: a start condition (s), a start byte (0000 0001), and an ACK repeat start condition (SR)
After the start condition is sent, the start byte (0000 0001) is sent ). in addition, the microcontroller can sample the SDA line at a low sampling rate to know that one of the 7 0s of the starting byte is detected. after detecting the SDA low level, the microcontroller can switch to a higher sampling rate to detect repeated start conditions for synchronization. generates a response-related clock pulse after the start byte. the device cannot reply to the start byte.