51 Interrupt priority and interrupt nesting for single-chip microcomputer

Say the most basic, the old 51 single-chip microcomputer (80C51 series) has 5 interrupt source, 2 priority, can achieve two level interrupt service nesting. Now many of the expanded 51 microcontroller already has 4 priority (or more) and more interrupt sources.

Before I talk about interruptions, I'll start by defining priorities and understanding what priorities are, and the subsequent elaboration is easy to understand. In fact, many people confuse the meaning of priority, so they feel confused.

There are two priority levels for interrupts: query priority and execution priority.

What is the query priority level? We see from datasheet or book The default (IP register does not set, 00H after power-on reset) Priority:
External Interrupt 0 > Timer/Counter 0 > External Interrupt 1 > Timer/Counter 1 > Serial Interrupt
or int0,timer0,int1,timer1,serial port or INT0, T0, INT1, T1, UART
or Px0>pt0>px1>pt1>ps>

In fact, the query is the optimal level. The first query priority is not to be changed and set. This is a matter of interrupting priority queuing. When multiple interrupt sources produce interrupt signals at the same time, the interrupt arbiter chooses the order in which to prioritize which interrupt source to process. This has nothing to do with the nesting of interrupt service programs. When the CPU queries each interrupt flag bit, it will query according to the above 5 query priority order, when a number of interrupts simultaneously request, will first query to the high-priority query first level interrupt flag bit, but does not represent the high query priority interrupt can interrupt already and is executing the low query priority interrupt service.

For example: When the counter 0 interrupt and external interrupt 1 (by query priority, counter 0 Interrupt > External interrupt 1) arrives at the same time, it will enter the interrupt service function of timer 0, but if the interrupt service function of external interrupt 1 is in service, then no interruption can break it. Includes an external interrupt 0 counter 0 interrupt with a higher logical priority than it.

The execution priority of the interrupt is the setting of the IP register. In the case of 2 priority, a bit is 1, then the corresponding interrupt source is high priority, and 0 is the low priority.

There are three principles regarding the priority of interrupts:
1, the CPU receives several interrupts at the same time, first responds to the highest priority interrupt request;
2. The ongoing interrupt process cannot be interrupted by a new sibling or low-priority interrupt request;
3, the ongoing low-priority interrupt service, can be Gao Xing priority interrupt request interrupt;

If: There is more than one interrupt request in the same execution priority, there is an interrupt priority queueing problem. The interrupt priority queueing of the same execution priority is formed by the natural priority of the interrupt system hardware, and the order of precedence from high to low is:
External interrupt 0> Timing/Count 0> external Interrupt 1> Timer/Count 1> serial interface

For example: Setting IP = 0x10, that is, setting the string to the highest priority, the serial interrupt can interrupt any other interrupt service function implementation nested, and only the serial interrupt can interrupt the other interrupt service function. If the serial interrupt is not triggered, then the other interrupts remain logically prioritized, and cannot be nested between each other.

About interrupt nesting. It can be said that when an interrupt is executing, if the interrupt priority register IP is set in advance, an interrupt nesting occurs when a higher priority interrupt arrives, and if there is no setting, no nesting occurs, and if there is an interrupt trigger with the same priority, it is not in "continuous application", Instead, the corresponding interrupt flag position is the location of the IE register, and when the CPU executes the current interrupt, the query priority is re-queried for each interrupt flag bit to enter the corresponding interrupt.

Keep in mind that when IP is not set, the single-chip opportunity queues into the service according to the query priority (or all logical precedence). If you want an interrupt to respond first, set the IP to change the execution priority (or physical priority). It is important to note that when the IP is set, when the low execution priority interrupt is run, if there is a high execution priority interrupt is generated, the call into the high execution priority interrupt is nested. If you are writing a program in C and using a hosting group when you interrupt the service, be aware that two different execution priority interrupt Service programs do not use the same set of registers.

See two questions, as follows:
1 when each interrupt is low priority, if the overflow of timer 0 enters the interrupt. In this interrupt processing process, the external interrupt 0 is also triggered, then it is not to occur interrupt nesting?
2 If the timer 0 interrupts, enter the interrupt handler, this time the external interrupt 1 condition trigger condition is satisfied. Because the timer 0 natural priority is higher than the external interrupt 1, then the interrupt handler for timer 0 continues to execute. Assuming that the timer interrupt handler is executing, an external interrupt of 1 is triggered. If the condition disappears, will the program still go to the external interrupt 1 handler after the interrupt processing of timer 0 is finished?

Answer 1: In the case of the IP prior to setting the priority of external interrupt 0, the Cup will abort the timer 0 Interrupt service, into the external interrupt 0 service program, after the execution of the timer 0 Interrupt service program. Or not.
Answer 2: Will definitely enter the interrupt, external interrupt 1 of the trigger conditions will set the external 1 of the interrupt flag, even if the trigger condition of the external interrupt 1 disappears, will not clear the set of interrupt flag, so when the interrupt processing timer 0 is finished, The program determines that the interrupt flag for an external interrupt is 1 and still enters an external interrupt 1 handler, and only the external interrupt 1 handler executes the RETI instruction to remove the interrupt flag for the external interrupt 1 (which is why the interrupt returned using the RETI instruction instead of the RET replacement) ...

51 Interrupt priority and interrupt nesting for single-chip microcomputer