51 MCU program memory expansion

In the expansion of single-chip microcomputer, the expansion of program memory and data storage should be considered separately.

Memory is the most widely used extended chip in the single-chip microcomputer system. For 80C51 series single-chip microcomputer, because the space of program memory and data storage is independent in physical space, the extension methods are slightly different. This section describes the commonly used EPROM (usually ically programmable read-on)Ly memory), EEPROM (electrically erasable programmable read-onMemory extension methods such as ly memory.

Program memory is used to store the fixed programs and table constants that have been prepared and always kept. The program memory uses the program counter PC as the address pointer. Through the 16-bit address bus, the addressable address space is 64kb.

In the 80C51/87c51/89c51 Chip, The 4kb ROM/EPROM program memory (internal program memory) with the lowest address space is built in respectively. In the 8031 chip, there is no internal program memory, the EPROM must be extended externally. The address of 64 kB internal and external program memory in 80C51 series single-chip microcomputer is uniformly arranged. 8031 single-chip microcomputer does not have internal program memory, the address is from memory H ~ Ffffh is an external program storage space. Always grounded. For a single-chip computer with an internal ROM (5l, 52 series), the pin is connected to a high level so that the program starts to run from the internal ROM. When the Pc value exceeds the capacity of the internal ROM, it will automatically turn to the external program memory space. The external program memory address space is H ~ Ffffh: The movc command is used to access the program memory.

Currently, the typical EPROM chip is a series of 27 products:

Model capacity model capacity

27c16 2 k × 8 bits 27c128 16 K × 8 bits

27c32 4 K × 8 bits 27c256 32k × 8 bits

27c64 8k × 8 bits 27C512 64k × 8 bits

. 2.2 EPROM program memory extended instance

Figure 8-1 shows the connection circuit between the 8kb × 8 program memory 27c64 and the single chip microcomputer. This circuit is also called the minimum system of 8031. Through the analysis of this system, it is necessary to master the relationship between the connection of memory expansion circuit and the Operation Sequence of MCU external program memory, that is, the Data Bus D0 ~ of MCU ~ D7, address bus a0 ~ A15 and control signal, the signal connection between ale and extended EPROM, 74LS373, and the role of 74LS373 in the circuit.

In the figure, 74LS373 is an 8d latch with three-state output. It is grounded by three-state control. When the G end is connected to the 8031 ale, The 74LS373 locks down the 8-bit address signal and outputs it for the system.

27c64 is an 8 KB x 8-bit EPROM device with 13 address lines a0 ~ A12 input, which can distinguish 13-bit binary address information. These 13 address lines correspond to P2 port 8031 and p2.0 ~ P2.4 connection. When the 8031 System sends a 13-bit address, each unit in the 8kb memory of 27c64 chip is selected.

Data line connection: memory's 8-bit data line D0 ~ D7 connected to P0 port (p0.0 ~ Lifecycle 7 ). The MCU requires that the instruction code and data are read by the P0 port, and the digits are connected accordingly.

The 27c64 pin is the chip selection signal input. The low level is valid, indicating that the 27c64 chip is selected. The signal selection determines the location of the 8kb memory of the 27c64 chip in the 64kb space of the entire 8031 extended program memory. The system has only one 27c64 block, which is usually valid when it is grounded. According to the above circuit connection method, the memory occupied by 27c64 is memory H ~ 1fffh address space.

Connection of the control line:

(External program memory receiving refers to signal) (memory reading signal ).

The allowable signal of the ale address lock is usually connected to the address lock signal.

(MCU internal/external program memory selection signal) when using 8031, 8032, and should be grounded.

In addition, 27c64 and VPP end and end can be combined into a variety of 27c64 working methods (read, standby, write-as-you-go programming, proofreading, etc ), the method shown in the figure is read and standby. If the selected communication number is low, 27c64 is selected, that is, the program or constant in 27c64 is read. If the selected communication number is high, the 27c64 is in the low-power STANDBY state.

　

<> Extended instance

The electrically modified EEPROM chip can modify the content in its storage unit like Ram, and keep the program and data content in the storage unit unchanged after power failure like Rom, therefore, the electric rewrite EEPROM has been widely used in various applications. The following uses the eeprom2864a chip produced by Intel as an example to describe the electric rewrite EEPROM.

2864a is an electrically erased programmable read-only memory chip. Single + 5 V power supply with a maximum operating current of 160mA and a maintenance current of 60mA. The maximum read time is ns, and the write time is about 16 Ms. Therefore, the read and write speed of 2864a is slow. Due to the high-voltage pulse circuit required for programming, no additional programming voltage and writing pulse is required. The capacity of 2864a is 8 KB × 8 bits, so the chip has 8 data lines and 13 address lines.

The read operation of 2864a is the same as that of an ordinary EPROM. The difference is that bytes can be written online. 2864a will automatically erase the write unit before writing a byte instruction or data, so no special erasure operation is required. It can be seen that using 2864a is as convenient as using Ram.

After sending a byte write command to 2864a, 2864a locks the address, data, and control signal to start a write operation. The write time of 2864a is about 16 Mb. During this period, the signal of 2864a is in the low-level 0 state, indicating that data writing is currently in progress. Its data line is in the high-impedance state and is disconnected from the bus. It prohibits the CPU from writing new data during this period, but allows the CPU to perform other operations. Once a byte write operation is completed, 2864a will increase the signal to High Level 1, which notifies the CPU to write new data. In this case, the CPU can perform new bytes read/write operations on 2864a.

(1) data line connection

P0.0 ~ of 8031 ~ Io0 ~ of ipv7 and 2864a ~ Io7 is connected directly.

(2) Connection of address lines

P0.0 ~ of 8031 ~ Listen 7 through 74LS373 latches and 2864a address line of low 8-bit a0 ~ A7 connection. 8031 p2.0 ~ P2.4 and 2864a address lines with 5-bit high A8 ~ A12 direct connection.

(3) connection to the control line

The chip selection signal of 2864a is connected to p2.7 of 8031, And the reading signal is generated after the phase and phase of 8031, as shown in 8-2. This connection enables 2864a to be used both as program memory and as data storage. The idle signal of 8264a is connected to p1.0 of 8031 to determine whether to start writing new bytes. If the signal line is connected to int1 of disconnection 8031, You can query the idle status of 2864a by means of interruption. The interrupt knowledge is described in Chapter 7th.

This article is reproduced from newhua's 51 microcontroller program memory expansion
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