5502 there are four clock groups:
- C55x subsystem clock group
- Fast peripherals clock group
- Slow peripherals clock group
- External memory interface clock group
1. c55x subsystem clock group the clock group includes c55x CPU core, memory (daram and Rom), icache, and all CPU-related modules. The input clock of this group is a clkout3 signal. If it is in PLL mode, the clkout3 signal can be adjusted through the divider D0 and the multiplier M1; if it is in Bypass mode, the frequency of clkout3 is the frequency at which the clock module inputs the clock source and cannot be changed.
2. Fast peripherals clock group the clock group includes DMA, HPI, and counter (timers ). The input for this group is divider 1 (D1 ). The default split frequency of divider 1 is 4. You can change the split frequency to 1 or 2 by changing the plldiv1 bit of the plldiv1 register. 3. Slow peripherals clock group the group clock includes mcbsps, IIC, and UART. The input for this group is divider 2 (D2 ). The default split frequency of divider 2 is 4. You can change the split frequency to 1 or 2 by changing the plldiv2 bit of the plldiv2 register. The clock frequency of the slow peripheral clock group must be less than or equal to the frequency of the fast peripheral clock group. 4. external memory interface clock group this group includes the EMIF module and the external data bridge module ). The input for this group is divider 3 (D3 ). The default split frequency of divider 3 is 4. You can change the split frequency to 1 or 2 by changing the plldiv3 bit of the plldiv3 register. The clock frequency of this group must be less than or equal to the frequency of the fast peripheral clock group.
