6.6410 and 210 key interrupt programming

6.6410 and 210 key interrupt programming

The first is to open the 6410 floor schematic:

You can see that the OK6410 has six keys:

You can see that the pins for the OK6410 six keys are KEYINT1, KEYINT2, KEYINT3, KEYINT4, KEYINT5, and KEYINT6. Then search for the word in the schematic of the core board:

You can see that the key interrupt is interoperable with the pin of the GPN series register, followed by the information on the GPN series registers in the chip manual, with a focus on the GPN control register: Gpncon:

Here we use the key corresponding to the interrupt, need to be configured to interrupt the way, the corresponding GPN bit set to 10, interrupt function, that is, the need to set Keyint1-6 to interrupt function, that is, the gpncon corresponding to the first 12 bits set to 101010101010. This sets the corresponding gpn0-5 to the interrupt bit. Implementation code:

Above we have completed the initialization of the keys, so that the six keys corresponding to the bit set to the external interrupt function.

The next step is the initialization of the interrupt.

1. Set the key interrupt is on the falling edge, that is, the way the falling edge is triggered, that is, low level, the key bounce is the rising edge, that is, high level.

Register Eint0con0 required here:

By the schematic know KEYINT1-KEYINT6 the corresponding interrupt bit is XEINT0-XEINT5, which is triggered by the above setting from the falling Edge:

Set the falling edge trigger, then remove the previously shielded function, which is to enable the interrupt:

Shielded registers:

Here we need to remove the blocking function of the interrupt bit eint0-eint5, otherwise, even if an interrupt occurs, it will not be sent to the CPU. This is for convenience, do not go to set, directly assign the register to 0, that is, all interrupts to remove the shield:

When you unblock an external interrupt, it is an operation that enables the external interrupt to be interrupted:

The above two registers are to enable interrupt, each bit control an interrupt source, after the system resets the default value is 0, if needs to enable some interruption, needs to set the corresponding bit to 1=interrupt enabled.

As we know from above, our external interrupt 0-3 is the interrupt source 0, the external interrupt 4-11 is the interrupt source 1. So to enable the external interruption of six keys, you need to enable the No. 0 interrupt source and 1th interrupt source, the interrupt source belongs to the VIC0 Register group, that is, to vic0intenable 0-bit and 1-bit write 1, code implementation:

This enables external interrupts to also be completed.

Next, set the CPSR program status register to open the total interrupt control, because the previous learning is to turn it off.

Here if you follow the 2440 non-vector interrupt setting to the end, but not in 6410, because 6410 uses the vector interrupt mode.

Let's take a look at the flowchart of non-vector interrupt mode:

The above is a non-vector interrupt processing process, when the interruption occurs, will jump to the corresponding unified entrance, to execute the corresponding interrupt handler, most of the work is software to complete.

and 6410 of the vector interrupts, a lot of the work is done by the hardware, so the speed will be faster, schematic:

The above is the principle of vector interrupts.

So the next step is to interrupt the initialization, the corresponding interrupt handler (that is, the handler's function name) into the corresponding register. Here's the operation: find the corresponding register group first:

You can see that there are 32 registers belonging to the VIC0 group, and there are 32 registers belonging to the VIC1 group, just 64 registers, corresponding to 64 interrupt sources. The key 1 corresponds to the EINT0, which is the corresponding register 0x71200100.

Code:

Above is the interrupt handler for the key. However, in 6410 the default is no enable vector interrupt, it is first compatible, the default is non-vector interrupt, so 6410 to use the vector interrupt needs to be enabled. Note that 210 does not need to be enabled. The 24-bit control of the C1 register in the CP15. 6410 Enable code:

__ASM__ (

"MRC p15,0,r0,c1,c0,0\n"

"Orr r0,r0,# (1<<24) \ n"

"MCR p15,0,r0,c1,c0,0\n"

"Mrs R0,cpsr\n"

"Bic R0, r0, #0x80 \ n"

"MSR Cpsr_c, r0\n"

:

:

);

Above is the enable vector interrupt operation, here to complete the 6410 interrupt initialization operation.

Finally, the interrupt is processed.

Steps:

1. Save Environment
2. Interrupt Handling
3. Clear interrupts
4. Recovery Environment

1. Save the Environment:

__ASM__ (

"Sub LR, LR, #4 \ n"

"Stmfd sp!, {r0-r12, lr}\n"

:

:

);

2. Interrupt Processing:

3. The interruption is clear:

Register to clear the interrupt:

When the corresponding interrupt is generated, the corresponding interrupt bit is set to 1. From the notes of this register, if you write 1 to the corresponding interrupt bit, the interrupt is cleared. Here for convenience, we write all 1, clearing all interrupts.

We know that each vector interrupt corresponds to a register

Registers for the VIC0 group:

VIC1 Group Register:

Above is the 64 interrupt source corresponding to 64 registers, after these registers has the Register vicxaddress:

This register has two, vic0address and vic1address. For example, when a serial port interrupt is generated by the VIC0, the system will save the address of the interrupt handler to the Vicxaddress register in addition to the corresponding processing function.

When the interrupt is finished, clear the two registers to 0:

This completes the interrupt handler.

4. The final step is to clear the interruption:

"Ldmfd sp!, {r0-r12, pc}^ \ n"

The procedure to complete the interrupt handler is completed here, and the final part of the code is as follows:

...

Note that although the interrupt handler is complete, it cannot be burned to the Development Board. This is because as with the 2440 case, our start. Only the stack of the SVC pattern is initialized in S, and the stack of the IRQ pattern is not initialized. So finally we have to initialize the stack of the IRQ:

You can see that the program is working in SVC mode at the beginning, while our key interrupt is working in IRQ mode. We need this to work in the IRQ mode stack in order for the program to run properly. To set the system to work in IRQ mode, you need to set the CPSR mode bit to 10010:

Implementation code:

The cpsr_c here is the end of the CPSR register at 8 bits:

The value set here is 0xd2=0b 11010010, and you can see that the value turns the interrupt on, and also sets the system to work in IRQ mode.

The final code is:

We set the value for the SP stack in IRQ mode, and then set the value for the SP stack under the SVC model. Recompile the burn write to the Development Board, when we press the corresponding button, you can see the corresponding LED light is on. If you press the first button to light, and then press the key does not respond, it is likely that the stack is not set.

This is the 6410 interrupt processing process, for 210 is the same operation, only 210 default is the open vector interrupt, do not have to set open, the others are the same.

6.6410 and 210 key interrupt programming