76.zynq-using PS to control DDR3 memory Read and write

The purpose of this article is mainly to use a concise method of DDR3 read and write, of course, this way every read and write needs CPU intervention, efficiency is relatively low, but this is the process of learning it.

As much as possible, this series of articles makes each experiment relatively independent, ensuring the integrity of the process as much as possible and ensuring the reproducibility of the experiment. However, the use of the module or IP specific role and usage is not guaranteed to repeat the detailed introduction.

The development Board used in this article is compatible with Zedboard
PC Development Environment Version: Vivado 2015.4 Xilinx SDK 2015.4

Build a hardware system new Vivado project

Select Zedboard

New Block Design

Add Zynq PS

Click Run Block Automation to have Vivado automatically configure the Zedboard related default information, click OK

Double-click Zynq, where you can remove some unused peripherals

Set Block Design

Right-click on block design, select Create HDL wapper complete, right click on block design, select Generate Output prouducts, select Generate click Generate in the popup dialog box When Bitstream is complete, select File->export->export hadfware, select the Include Bitsteamfile, Launch SDK, Export the hardware architecture to the software engineering program to write a new Hello project

DDR3 's address

After the build, in the Mem_demo_bsp->ps7->cortexa9_0 path, open xparameters_ps.h This header file, this header file is cortexA9 can directly control the peripheral address of the macro definition. You can find the address of the DDR in the inside, you can see the following code:

/* Canonical definitions for DDR MEMORY */
#define XPAR_DDR_MEM_BASEADDR 0X00000000U
#define XPAR_DDR_MEM_HIGHADDR 0x3fffffffu

We're going to use this address to read and write to DDR3.

Read-write Operation function

Under the Mem_demo_bsp->ps7->cortexa9_0 path, open the Xil_io.h header file, which is a memory map that cortexA9 can directly control or that maps to an IO in the address space. You can see the following code inside:

Read data from an address
U8 Xil_in8 (INTPTR Addr);
U16 Xil_in16 (INTPTR Addr);
U32 Xil_in32 (INTPTR Addr);

Write data to an address.
void Xil_out8 (INTPTR Addr, U8 Value);
void Xil_out16 (INTPTR Addr, U16 Value);
void Xil_out32 (INTPTR Addr, u32 Value);

OK, with this you can simply continue to write the DDR operation

Code implementation

 #include "stdio.h"#include "platform.h"#include "Xparameters.h"#include "Xparameters_ps.h"#include "xil_printf.h"#include "xil_io.h" #define DDR_BASEARDDR xpar_ddr_mem_baseaddr + 0x10000000int main () {init_platform (); int i; int rev; xil_printf ( "Hello world\n\r"); for (I=0; I<32; i++) {xil_out32 (ddr_basearddr+i*4,i);} for (I=0; I<32; i++) {rev = xil_in32 (ddr_basearddr+i*4); xil_printf ( Span class= "hljs-string" > "the address at%x data is:%x \n\r", ddr_basearddr+i*4, rev.); } cleanup_platform (); return 0;}         

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Burn Write Test

The results of the serial terminal are as follows:
Hello World
The address at 10000000 data is:0
The address at 10000004 data is:1
The address at 10000008 data is:2
The address at 1000000C data is:3
The address at 10000010 data is:4
The address at 10000014 data is:5
The address at 10000018 data is:6
The address at 1000001C data is:7
The address at 10000020 data is:8
The address at 10000024 data is:9
The address at 10000028 data is:a
The address at 1000002C data is:b
The address at 10000030 data is:c
The address at 10000034 data is:d
The address at 10000038 data is:e
The address at 1000003C data is:f
The address at 10000040 data is:10
The address at 10000044 data is:11
The address at 10000048 data is:12
The address at 1000004C data is:13
The address at 10000050 data is:14
The address at 10000054 data is:15
The address at 10000058 data is:16
The address at 1000005C data is:17
The address at 10000060 data is:18
The address at 10000064 data is:19
The address at 10000068 data is:1a
The address at 1000006C data is:1b
The address at 10000070 data is:1c
The address at 10000074 data is:1d
The address at 10000078 data is:1e
The address at 1000007C data is:1f

76.zynq-using PS to control DDR3 memory Read and write