8th, asynchronous parallel Interface timing design

"Learning purpose"

① learn the sequential operation of asynchronous parallel interface, and grasp the method of timing description of the synchronous port;

② Review the Verilog HDL description method and simulation method of inout bidirectional port;

③ the simulation method of receiving/sending two-way communication.

"knowledge of asynchronous and associated ports"

(1) Application and advantages and disadvantages of asynchronous synchronous port

The biggest flaw of the same port: has the multi-channel data bus and the address bus, because the line length, uses the line material to have the difference, therefore, when the signal frequency increases, will have the line delay different phenomenon, thus causes each road signal arrives the target port the time different, causes the signal to appear the massive burr and the instability.

Secondly, the same port occupies more I/O port, and it is difficult to meet the high frequency signal transmission requirements.

Therefore, when the signal frequency is very high, often from the use of serial transmission, and when the frequency is low (only a few 10 MHz), you can use the parallel port transmission mode.

(2) Sequence diagram of the write operation

Figure 1 Write Operation timing Diagram

Asynchronous parallel port asynchronous refers to the host does not output the clock signal to the slave as the communication between them, the synchronous port of the asynchronous parallel port refers to the main-slave data line (this example is 16) and the address line has multiple root (this example is 8), and the master-slave data interaction between the two is concurrent.

As shown in 1, the Cs_n is an asynchronous chip-selectable signal, the low-level is active, the rd_n is the read enable signal, the low level is active, the We_n is the write enable signal, the low level is active, the data is the data bus, the bit width is 16bit;addr to address bus, and the bit width is 8bit.

1, when the cs_n is low, the FPGA is selected by the host piece, when the FPGA detects that the we_n signal is pulled down, that is, into the asynchronous and write state, the data bus into the FPGA, The data is stored on the specified storage space (e.g. RAM, FIFO, etc.) according to the address value on the addr address bus.

(3) Sequence diagram of the read operation

Fig. 2 sequence diagram of read operation

Figure 2 is the asynchronous synchronous port read operation timing, when the cs_n is low, the FPGA is selected by the host piece, when the FPGA detects that the rd_n signal is pulled low, that is, to enter the asynchronous read state of the port, The FPGA reads the data from the specified storage location on the value of the address on the addr address bus and sends it on to a data data bus for the host device to read.

"Code Implementation"

Asynchronous parallel port, although there is no synchronous clock signal, but also can not be described in the form of combinatorial logic, because the timing logic has a higher stability, can give the data collection to sufficient settling time and retention time, so that the read/write operation can be stable after the data stability. The output of the combinational logic circuit changes with the input signal in real-time, if the signal between the main-slave is slightly unstable, it will cause the error of the read/write operation.

Therefore, this example still uses sequential logic circuit-based description, the Cs_n, Rd_n, wr_n and other input signals to the SCLK system clock domain, and then under the control of the system clock SCLK in order to work. Of course, like this asynchronous clock domain there is a metastable phenomenon, so in order to reduce the probability of metastable, we use "beat" way to stabilize the input signal, unified with the SCLK system clock to the input signal more than two beats (two clock cycle delay).

The above analysis indicates that the code to be designed should contain the following three parts:

(1) Use the system clock SCLK to give the input signal more than two beats, stabilize the input signal;

(2) Asynchronous write operation module (external to FPGA);

(3) Asynchronous interface read operation module (including output operation of InOut port).

"About inout two-way port description and testing"

Figure 3 InOut bidirectional port test model

3, shows the test model used in this example, for the FPGA chip, the asynchronous read operation of the port is the data output, the write operation is the input of the data, and for the test excitation end, the asynchronous synchronous write operation is the data output, read operation is the input of the data.

Therefore, the FPGA end should be programmed as follows:

InOut Tri [15:0] data,//bidirectional data bus

Assign data = (cs_n_r[2]==1 ' b0 && wr_n_r[2]==1 ' b1 && rd_n_r[2]==1 ' B0)? Read_data:16 ' hzzzz;//read operation output data

For write input data, the data bus is fed directly to the FPGA register.

The test excitation end should be programmed as follows:

Tri [15:0] data;

reg [15:0] Data_reg;

Assign data = (wr_n==1 ' B0)? Data_reg:16 ' hzzzz;//write operation output data

For the read operation input data, the data bus can be read directly.

"Testbench Building"

(1) The time delay tasks such as settling time, holding time, data sampling period and reading wait time are declared so as to simulate the reading and writing timing of asynchronous synchronous port;

(2) Read Data task

(3) Write Data task

(4) Simulation Process Control

"Experimental Results"

Figure 4 Beat time delay 60ns

Figure 5 Setup time, data acquisition time, hold time

Figure 6 Read wait time

Figure 7 Transcript window information

Figure 8 Simulation waveform overall diagram

8th, asynchronous parallel Interface timing design