9.S5PV210 's clock system

1. Clock domain: MSYS, Dsys, PSYS
(1) because the s5pv210 clock system is more complex, the internal peripheral module too many, so the entire internal clock divided into 3 chunks, called 3 domains.
(2) MSYS:CPU (Cortex-a8 Core), DRAM controllers (DMC0 and DMC1), Iram&irom
(3) Dsys: All the modules related to video display, codec, etc.
(4) PSYS: And the internal various peripheral clocks, such as serial port, SD interface, I²C, AC97, USB and so on.
(5) Why the internal divided into 3 domains, how to divide? Since 210 of these modules work with each other, the clock rate difference is too large, so it is necessary to put the high-speed together, relatively low-speed put together.

2. Clock Source: Crystal oscillator + Clock generator +pll+ crossover circuit
(1) s5pv210 External 4 Crystal Oscillator interface, the design of the board hardware can be based on the need to determine where to connect crystal oscillator. After the crystal oscillator is connected, the corresponding module can generate oscillation and produce the original clock. The original clock then passes through a series of filter switches into the corresponding PLL circuit to multiply the high frequency clock. The high frequency clock is then divided into the internal modules of the chip. (some modules, such as the inside of the serial port and further frequency divider for re-use)

3, PLL:APLL, MPLL, EPLL, VPLL
Apll:cortex-a8 kernel Msys Domain
Mpll&epll:dsys PSYS
Vpll:video Video related modules

4, s5pv210 clock domain detailed
1.6.3.1, Msys domain:
ARMCLK: The clock that works for the CPU core, the so-called frequency.
High-frequency clocks in the Hclk_msys:msys domain for use with DMC0 and DMC1
Low frequency clock in Pclk_msys:msys domain
Hclk_imem: Used for Irom and Iram (collectively imem)

1.6.3.2, Dsys domain:
High frequency clock in Hclk_dsys:dsys domain
Low frequency clock in Pclk_dsys:dsys domain

1.6.3.3, Psys domain:
High frequency clock in Hclk_psys:psys domain
Low frequency clock in Pclk_psys:psys domain
Sclk_onenand:

Summary: 210 internal peripherals are connected to (internal Amba bus) bus above, Amba Bus has 1 high-frequency branch called AHB, there is a low-frequency branch called APB. Each of the above fields have their corresponding hclk_xxx and pclk_xxx, where hclk_xxx is the XXX domain AHB the operating frequency of the bus, pclk_xxx is the xxx domain of the APB bus operating frequency.
Each peripheral inside the SOC is actually hanging on the bus, which means that the peripheral clock comes from the bus he hangs on, such as the serial UART is hung on the APB bus in the PSYS domain, so the clock source of the serial port is Pclk_psys.
We can determine the specific clock frequency for each of our peripherals by remembering and analyzing these clock domains and bus values.

1.6.3.4, typical values for each clock (default value, value set in Irom)
(1) When the 210 just power on, the default is the external crystal + internal clock generator generated by the 24MHz frequency of the clock directly to ARMCLK, then the system's main frequency is 24MHz, running very slow.
(2) The Irom code executes the 6th step in the initialization of the clock system, this gives the system a default recommended operating frequency. This clock frequency is recommended by Samsung for the best frequency of 210 operating performance and stability.
(3) Typical values of each clock:
? Freq (ARMCLK) = + MHz
? Freq (Hclk_msys) =-MHz
? Freq (HCLK_IMEM) = + MHz
? Freq (Pclk_msys) = + MHz
? Freq (Hclk_dsys) = 166 MHz
? Freq (Pclk_dsys) =-MHz
? Freq (Hclk_psys) = 133 MHz
? Freq (Pclk_psys) = MHz
? Freq (Sclk_onenand) = 133 MHz, 166 MHz

9.S5PV210 's clock system