A 23-point Experience Summary based on FPGA/CPLD Application Design -- About the VHDL code style

From FPGA/CPLD Application Design Example 1

2. Use lowercase letters for all signal names, variable names, and port names, and uppercase letters for constant names and user-defined types.
4. Use meaningful signal name, variable name, Port name, and parameter name.
6. The signal name length should not be too long, and strive to be concise and clear.
8. Use CLK as the prefix of the signal name or signal name for the clock signal (when multiple clocks exist in the design ).
10. For signals from the same driver source, use the same name in different sub-modules. This requires that the name of the connection between the top-layer sub-modules be defined in the overall design of the chip. The signal of the port and the connection port should use the same name as possible.
12. For low-level valid signals, a lowercase letter B or N should be added as an underline, for example, a2b_reg_n.
14. For reset signals, RST is used as the signal name. If it is low-level, rst_ B or rst_n.
16. Try to abide by the conventions that the industry is used. For example, * _ r indicates the register output, * _ A indicates the asynchronous signal, * _ PN indicates the signal used in the nth cycle of the multi-cycle path, and * _ NXT indicates the signal before the lock, * _ z indicates a three-state signal.
18. A file header should be included at the beginning of the source file and batch file. It generally includes the following content: file name, designer, Module name, module implementation function overview, simulation software used, software running platform, integrated tools used, and tool running platform, file Creation Time, file modification time.
20. Use a brief statement to comment out all processes, functions, port meanings, signal meanings, variable meanings, signal groups, and variable groups.
22. Each row of statements runs in a separate line.
24. Indentation is used to improve the readability of the continued and nested statements.
26. In the RTL source code design, the names of any element cannot contain the reserved characters of VHDL and Tilde.
28. When declaring the module port, we recommend that you use the following sequence: CLK, RST, enables other control signals, data and address signals of the input signal, and then CLK, RST, enables other control signals, data and address signals.
30. In the sample module, explicit name ing is used instead of location-related ing.CodeReadability and avoid compilation line errors.
32. If the same piece of code needs to be repeated multiple times, use the function whenever possible. If possible, make the function generic.
34. Use loop statements and register groups as much as possible to improveSource codeReadability.
36. Only IEEE-defined standards are used for data types during code writing.
38. Do not use numbers directly in the design. As an exception, use 0 and 1. We recommend that you use parameter definitions instead of direct numbers.
40. Do not use the embedded dc_shell command in the source code.
42. Avoid instantiating a specific gate circuit during design.
44. Avoid lengthy logic and expressions.
46. To avoid using an internal tri-state circuit, we recommend that you use a multi-path selection circuit instead of an internal tri-state circuit.