About Avalon Bus Understanding (Collation)

1, a system based on the Avalon interface will contain a number of functional modules, which are Avalon memory mapping peripherals, often referred to as Avalon peripherals. The so-called memory-mapped peripherals refer to peripherals and memory using the same bus to address, and the CPU uses the instructions to access the memory to access the I/O devices. In order to be able to use an I/O device, the address space of the CPU must be reserved for I/O devices.

2,avalon Peripherals are primary peripherals and slave peripherals, and the peripherals that can initiate bus transmissions on the Avalon bus are the main peripherals, which can only respond to the Avalon bus transmission from the peripheral, not the bus transmission. The primary peripheral has at least one primary port connected to the Avalon switching architecture, and the primary peripheral can also have a slave port, allowing the peripheral to respond to bus transmissions originating from other main peripherals on the bus.

The 3,avalon switching architecture is an automatically adjustable structure that makes optimal adjustments as designers design. You can see that peripherals and memory can have different data widths, and these peripherals can operate at different clock frequencies. The Avalon switching architecture supports multiple primary peripherals, allowing multiple primary peripherals to communicate simultaneously on different slave peripherals, increasing the bandwidth of the system. The implementation of these functions is implemented by the logic of address decoding, signal multiplexing, arbitration, and address alignment in the Avalon switching architecture.

The 4,avalon interface defines a set of signal types (chip selection, read enable, write enable, address, data, etc.) that describe the address-based read-write interface on the primary/slave peripheral. Avalon Peripherals Use only the necessary signals to interface with their kernel logic, eliminating the need for other signals that add unnecessary overhead.

The 5,avalon signal type provides a superset of other bus interfaces, such as the most isolated SRAM, ROM, and flash chip pins that can be mapped to the Avalon signal type, allowing the Avalon system to connect directly to these chips. Similarly, most wishbone interface signals can also be mapped to the Avalon signal type, making it easy to integrate the wishbone kernel into the Avalon system.

There is no direct connection between the primary port and the slave port of the 6,avalon, and the primary and slave ports are connected to the Avalon switching architecture, which is performed by the switching architecture to complete the signal transfer. During transmission, the signals passed between the primary port and the switching architecture can vary greatly from the switching architecture to the signal passed between the ports. Therefore, when discussing the Avalon transfer, the master-slave port must be distinguished.

7,avalon signal type description for primary and slave ports

From the port signal 1

From the port signal 2

Primary Port Signal 1

Primary Port Signal 2

8, the signal types in the table are high-active. The Avalon interface also provides a low-active version of each signal type, which is represented by adding _n after the signal type name. such as Irq_n, Read_n and so on. This is useful for interfacing with low-level, off-chip logic.

The 9,avalon interface specification does not specify a naming rule for signals on Avalon peripherals, and the names of the signals on the Avalon peripherals can be the same as the signal type names, or also follow the system-level naming conventions.

10, can also be out-of-chip asynchronous peripherals, such as off-chip storage devices, with the system switching fabric port, but need some design considerations. Due to the synchronous operation of the Avalon switching architecture, the Avalon signal is flipped only at the time interval of the Avalon interface clock. Furthermore, if the asynchronous signal is directly connected to the input of the Avalon switching architecture, the designer must ensure that the signal is stable on the rising edge of the clock.

The 11,avalon interface has no fixed or highest performance. The interface is synchronous and can be driven by the clock of any frequency provided by the switching architecture. The highest performance depends on the design of the peripherals and the implementation of the system. Unlike the conventional shared bus implementation specification, the Avalon interface does not specify any physical and electrical characteristics.

12, a master-slave port pair in the primary and slave ports can have different transport properties. When the Avalon switching architecture communicates with the primary/slave port, the properties specified by the port are used, and the property conversions from the primary port to the slave port are necessary. This allows the Avalon peripherals to be designed independently of the other peripheral properties in the system.

13, dynamic address alignment refers to the service of the Avalon switching architecture to dynamically manage the transferred data when transferring between master and slave port pairs with different data. When the primary port is addressed from the port using dynamic address alignment, all data from the port is continuously aligned in bytes in the address space of the primary port. If the primary port data is wider than the width from the port, the high-level byte of the primary port should be the next address from the port address space. For example, a 32-bit primary port uses dynamic address alignment to read data from a 16-bit slave port, and the Avalon switching architecture performs two read transmissions from the port side, and then provides 32-bit slave port data to the primary port. If the data width of the primary port is narrower than from the port, the Avalon Interchange schema handles the byte segment from the port appropriately. The Avalon switching architecture provides only the appropriate byte segments from the port to the primary port when the primary port is read-transmitted. In the primary port write transfer, the Avalon switching architecture automatically resets the byteenable signal to the appropriate byte segment from the port side.

14, example of dynamic address alignment

15, when the primary port is addressed from the port using local address alignment, all from the port data and the primary port address boundaries are aligned. When the primary port reads data from the port from a narrower data width, the data bits from the port are mapped to the low bits of the primary port data, while the primary port data is high bit 0. High bit bits are ignored during transmission. For example, the 16-bit primary port reads 8-bit from the port, and the readdata signal is in the form of 0x00xx, where xx represents valid data. The primary port cannot use local address pairs to access the data width of the slave port that is wider than its own.

About Avalon Bus Understanding (Collation)