About I2C bus

1. I2C Protocol
Two two-way serial lines, one data line SDA, and one clock line SCL.
The data transmitted by SDA is transmitted at a large end. Each transmission is 8 bits, that is, one byte.
Multimastering is supported, and only one master can be created at any time point.
Each device on the bus has its own ADDR, a total of 7 bits, and the broadcast address is all 0.
The system may have multiple chips of the same type. For this reason, ADDR is divided into a fixed part and a programmable part. The details depend on the chip and the datasheet.

1.1 I2C bit transmission
Data transmission: in High-Power cases, if the SDA line remains stable, the SDA is transmitting data bit;
If SDA changes, it indicates the start or end of a session (later)
Data Change: The transmitted bit can be changed only when the SCL is low.

 1.2 I2C start and end signals
Start signal: in high-power mode, SDA switches from high level to low level to start transmitting data.
End signal: in high-power mode, SDA changes from low-level to high-level and ends data transmission.

 

1.3 I2C response signal

Each time the master sends 8-bit data, it waits for the slave ack.
That is, in the case of 9th clock, if the Ack is sent from the IC, the SDA will be pulled down.
If there is no ACK, SDA will be set to high, which will cause the master to restart or stop the process, as shown below:

 1.4 I2C write process
The standard process for writing registers is:
1. The master initiates start
2. The master sends I2C ADDR (7bit) and W operations 0 (1bit), waiting for ACK
3. Slave sends ACK
4. The master sends reg ADDR (8bit) and waits for ACK
5. Slave sends ACK
6. The master sends data (8 bit), that is, to write the data in the register, wait for ACK
7. Slave sends ACK
8. Steps 6th and 7th can be repeated multiple times, that is, multiple registers can be written in sequence.
9. The master initiates stop

Write a register

 Write multiple registers

 

 1.5 I2C read Process

The standard process for reading registers is:
1. The master sends I2C ADDR (7bit) and W operations 1 (1bit), waiting for ACK
2. Slave sends ACK
3. The master sends reg ADDR (8bit) and waits for ACK
4. Slave sends ACK
5. The master initiates start
6. The master sends I2C ADDR (7bit) and r operation 1 (1bit), waiting for ACK
7. Slave sends ACK
8. Slave sends data (8 bit), that is, the value in the register.
9. The master sends ack messages.
10. Steps 8th and 9th can be repeated multiple times, that is, multiple registers can be read sequentially.

Read a register

 Read multiple registers

 2. I2C implementation of PowerPC

There are 6 I2C control registers in the ccsr of the mpc8560.

 

2.1 i2cadr Address Register

The CPU can also be an I2C slave. the I2C address of the CPU is specified by i2cadr.

 2.2 i2cfdr frequency setting register

The serial bit clock frequency of SCL is equal to the CCB clock divided by the divider.
Used to set I2C bus frequency

2.3 i2cr control register

 
Men: module enable. When set to 1, the I2C module enables
Mien: module interrupt enable. I2C interrupt enabling when set to 1.
Msta: Master/Slave Mode. 1 master mode, 0 slave mode.
When 1-> 0, the CPU initiates a stop signal
When 0-> 1, the CPU initiates the start signal
Run the following command to select the mode select.0 receive mode and 1 transmit mode.
Txak: Transfer acknowledge. When set to 1, the CPU will send ACK at 9th clock to lower SDA.
Rsta: Repeat start. When set to 1, the CPU sends repeat start
Bcst: Set 1, and the CPU receives broadcast information (the slave ADDR of the information is 7 0)

2.4 i2csr Status Register

OLAP: 0 byte Transfer is in process
1 byte Transfer is completed

Maas: When the CPU is used as the slave, if the i2cdr matches the slaveaddr in the session, this bit is set to 1

MBB: 0 I2C bus idle
1 I2C bus busy

Mal: If 1 is set, the arbitration fails.
Bcstm: If set to 1, it indicates that the broadcast information is received.

SRW: When Maas is set, SRW indicates the value of the R/W command bit of the calling address, which is sent from the master.
0 slave receive, Master writing to slave
1 slave transmit, Master reading from slave

MIF: module interrupt. The MIF bit is set when an interrupt is pending, causing a processor interrupt request (provided i2cr [mien] is set)

Rxak: if it is set to 1, Ack is received.

2.5 i2cdr data register

 
This register stores the data that the CPU will transmit.

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