Aging testing of Electronic Components

In order to achieve a satisfactory pass rate, almost all products must first aging before leaving the factory. How can manufacturers improve their efficiency without reducing their aging time? This article introduces a new scheme for functional testing during the aging process to reduce and shorten the cost and time problems brought about by the aging process.
In the semiconductor industry, the aging of devices has been controversial. Like other products, semiconductors may be faulty at any time for various reasons. Aging means to overload semiconductors and cause defects to appear in a short time to avoid early failures. Without aging, many semiconductor products may cause many problems in use due to the complexity of devices and manufacturing processes.
Defects that occur within a few hours to a few days after use (depending on the maturity of the manufacturing process and the overall structure of the device) are known as early failures, after aging, the device basically requires 100% to eliminate faults caused by this period of time. The only way to accurately determine the aging time is to refer to the aging fault and fault analysis statistics collected previously, while most manufacturers want to reduce or cancel aging.
The aging process must ensure that the factory products meet the reliability requirements of users. In addition, it must provide engineering data to improve the performance of devices.
Generally, the aging process uses both the working environment and the electrical performance to perform rigorous tests on the semiconductor device so that the fault can occur as soon as possible. The typical semiconductor life curve is shown on the right. As shown in the figure, all major faults occur in the first and tenth stages of the device life cycle. Aging is the process of accelerating the first 10% parts of the device's life, forcing early failures to appear in a shorter period of time, usually hours instead of months or years. Not all Semiconductor manufacturers need to aging all devices. Due to the knowledge of the production process, the failure prediction value obtained by statistics can be obtained in advance. If the actual failure rate is higher than the expected value, aging is required to improve the actual reliability to meet user requirements.
The aging method introduced in this article is almost the same as that introduced 10 years ago. The difference is that how to make better use of the aging time. Increasing the temperature, increasing the input of dynamic signals, and increasing the operating voltage to a normal value or higher are common methods to accelerate the occurrence of faults. However, if testing is performed during aging, the aging cost can be apportioned to the function test, and some useful information can be collected through the fault point monitoring, saving the overall production cost. In addition, the statistics also show whether the time required to identify all early failures of a device is appropriate.

Past aging systems
The first reason for aging is to improve the reliability of semiconductor devices, so far there are no other alternatives. Aging is still carried out in a high greenhouse (usually around 125 ℃), and electronic bias is added to the device. In most cases, dynamic driving signals are also used.
Many companies want to reduce or completely cancel aging, but they cannot find other reliable alternatives to remove early failures before the product reaches the customer, so it seems that aging will continue to exist for a long time. Semiconductor manufacturers also hope to do more with aging, rather than wasting valuable time passively waiting for components to be sent for aging.
The Design of aging systems in the past is relatively simple. 10 years ago, aging was to insert a device into the aging board, then put the aging board into the aging chamber, add DC bias (static aging) to the aging board, and increase the temperature, after 168 hours, the device will be taken out for testing. If the performance remains intact after the 100% test, the device quality can be ensured and sent to the user.
If the device fails during aging, it will be sent to the fault analysis laboratory for analysis, which may take weeks. The data provided by the lab will be used to make minor adjustments to the design and production processes, but it also shows that the production has been in progress for several weeks prior to taking remedial measures for possible serious faults. At present, engineers have found some ways to aging devices with high coverage rate due to long-time errors, and even perform some tests on the devices. Unfortunately, no one can solve the fundamental problem of aging, that is, reducing costs and time. As a result, semiconductor manufacturers have adopted another aging method: functional testing during aging.
Why do we need to perform tests during aging?

There are many reasons for the significance of semiconductor testing in the aging phase. Before exploring these reasons, we must first clarify the true meaning of testing.
Generally, high-speed automatic testing equipment is used for semiconductor testing. The semiconductor is tested on a test bench with adjustable electrical performance. It also performs functional (logic) and parameter (speed) tests beyond the nominal performance range. parameters such as the signal lifting time can be accurate to the second level. It may be because only one device in a controllable test environment acts as an electrical load, so the signal conversion is fast and real device response parameter measurement can be performed.
However, to increase the product output, it is best to aging as many devices as possible at the same time. To meet this requirement, multiple devices can be mounted on a large printed circuit board called an aging board. All the devices on the board are connected in parallel. The physical and Electrical Properties of a large aging board cannot be compared with that of a small test bench that tests only one device, because the capacitive and inductive load of the aging board can cause trouble in speed testing. Therefore, we usually cannot use aging to test all functions. However, in some cases, it is also possible to perform speed tests in aging environments using special system design technologies.
The "test" in the aging system can refer to any aspect, from testing the basic signal of each pin of each device, to testing almost 100% of all devices on the Aging board, all of this depends on the complexity of the device and the aging testing system selected. It can be said that a 100% functional test can be performed on any device, but this method may reduce the device density on the Aging board, thus increasing the overall cost and reducing the output.

The following are the benefits of testing during aging:
1. moving time-consuming functional testing to aging can save time for expensive high-speed testing instruments. If only Parameter Tests and few functional tests are performed after aging, more devices can be tested using existing devices. This alone can offset the costs incurred by using the aging test scheme.
2. The actual aging time to reach the expected failure rate is relatively shorter. In the past, the first batch of devices had to take up to 168 hours for aging. This was the standard start time for people to expect all early failures, and this was entirely due to the absence of new device data. In the next six months, this time will be shortened until the actual aging time is obtained by experiment and error analysis. During aging testing, you can check the real-time records generated by the aging system to detect faults in a timely manner. Understanding the aging time as soon as possible can increase production and reduce device costs.
3. Timely feedback on the production process. Device faults sometimes correspond directly to a manufacturing process or a production device. When a fault occurs, you can immediately learn the information to solve possible Process Defects and avoid creating a large number of unqualified products.
4. Ensure that the aging running conditions are consistent with expectations. By monitoring each device on the Aging board, you can replace the broken device at the beginning of aging, so that the user can ensure that the aging board and aging system run as expected, there is no waste of capacity.
Aging Test System Type
At present, there are a variety of aging testing system implementation methods on the market. In addition to general-purpose products manufactured by aging system manufacturers, semiconductor manufacturers have also developed some internal systems for their own use. Most systems use computers as hosts for data collection and basic circuit control. Some non-computer systems only use LEDs as status indicators and need to collect data manually.
To independently test each device on the Aging board, each device must be electrically isolated from other devices under the control of the aging system. Memory parts are very suitable for this scenario, because they are designed to be used in clustering mode and carry multiple-channel communication numbers, while logical devices may not be able to use the selected communication numbers, this makes it harder to design general logic tests in aging systems. Therefore, it is normal to have different logical aging systems for different device types.
There are two main types of aging testing systems: logical devices and memory. Logical device testing systems can be divided into two categories: parallel and serial; similarly, memory testing systems can also be divided into two categories: non-volatile and non-volatile.
Logical Device aging test
The aging test of logical devices is the most difficult among the two types of systems, because the logical product has many features and the communication pin may not be selected on the device. To adapt an aging testing system to all types of logical devices, a large number of input and output leads are required so that the system can generate a variety of signals that are usually required for multiple pin devices. The aging system also has a drive board, which is used as the pin driver for each signal path. It generally adopts a large drive current to overcome the load characteristics of the aging board.
The output signal must be able to process any device type that requires aging. If there is a problem with loading the aging board, you can separate it into two or more signal areas, but this requires doubling the number of signal lines on the driver board. Most parallel output signals are generated using specialized logic, pre-programmed EPROM, or reprogrammed and downloadable SRAM. The advantage of using SRAM is that the aging system can be applied to a variety of products using computer repeated programming.
There are two main methods to test the aging of logical devices: parallel and serial, which refer to the system input or monitoring methods. Generally, all logic device testing systems transmit a large amount of signals to the device in parallel. However, in this way, monitoring cannot separate each device on the Aging board.
‧ Parallel testing
Parallel testing is the fastest method for device testing during aging. This is because multiple signal lines are connected to the input and output ends of the device, which maximizes data transmission, the input end of the I/O line is controlled by the system test part. There are three basic methods for parallel testing: Single-pin signal return and multi-pin signal return for each device.
‧ Single-choice method for each device
If the components on the Aging board can be separated from other devices, the system can connect them to each device by selecting a method. For example, if the chip selection pin is used, all devices are connected in parallel, select only one device at a time to generate a return signal (figure 2 ). The system provides dedicated device selection signals. During the test, one device is selected at a time. during aging, all devices can be selected and receive the same data at the same time.
In this way, each device is selected in turn, and a large amount of data between the device and the aging system is transmitted through parallel bus. The limitation of this method is that the selected device must overcome the capacitive and inductive loads of the aging board and other unselected devices, which may reduce the data transmission speed of the device on the bus.
‧ Single-pin signal return
In this method, all devices are connected in parallel, except that each device has a signal return pin, and all devices are in the working state at the same time, the system selects the monitored device and reads the corresponding signal return line. This method is similar to the serial test method, but the signal pins generally detect the logic level or the pulse mode that can be compared with the reserved value. The detected signal usually indicates the internal self-check status of the device. It exists in the device for testing. If the device does not perform self-check, it is simply a pin that the system monitors, the test reliability will be greatly reduced.
‧ Multi-pin signal return
This method is similar to single-pin signal return, but more signals are returned from each device. Since each device has more signal return lines, This method requires multiple return monitoring lines. Because there must be a large number of response lines dedicated for this method, the overall cost of the system will increase dramatically. This method may be required for devices that do not have internal self-check and are very complex.
‧ Serial Testing
Serial testing is easier than parallel testing, but the speed is much slower. Except for the serial signal return lines of each device, each device on the Aging board is usually connected in parallel. This method is used for devices that have certain processing functions and can reflect various States through a signal return line. The data transmitted during testing must be decoded. Therefore, the aging Board should have a data processing system.
‧ RS-232C or equivalent agreement
A serial monitoring method is the use of full duplex RS-232C communication protocols on the Aging Board, and other supporting signals (such as clock and reset) of all devices are connected in parallel (Fig. 3 ). The RS-232C transmitter (txd) is typically connected to all devices, but also supports separation of aging Board areas for multiplexing for further transmission.
Each device returns a signal to an RS-232C acceptor (rxd) on the drive board, which can be reused on the drive board. The drive circuit transmits signals to all devices and then monitors the rxd line of the device. Each device is selected and the system compares the obtained data with the reserved value. This testing system typically uses a microprocessor on the drive Board to facilitate RS-232C communication and serve as a buffer for faulty data.
‧ JTAG)
The latest trend of aging of logical devices is defined in IEEE 1149.1. This method is also called the JTAG or boundary scan test. It adopts a five-wire (TCK, TDO, TDI, TMS and trst) Electronic protocol and can be comparable to the same line test method.
In this way, the JTAG test port and the entire system must be designed inside the device. The Circuit Used for JTAG testing on the device is a dedicated test port used to test the device. This test port can be used even after the device is installed on the user's terminal system and has started to work. Generally, the JTAG port uses a long serial cache chain to access all internal nodes. A certain function or feature of each cache device, so you only need to serially shift the status data of the cache device to the output end to access the certain state of the device.
The same technology can be used to program the device, but the data is serialized to the device through the JTAG port. The description of IEEE 1149.1 details the JTAG port operations.
Memory Aging
Memory Aging and testing lines are relatively simple to implement. All devices are written in a unified manner, and each device is selected separately to read the stored data and compare it with the original values. Because of its control and data collection software and fault data evaluation report algorithm, the memory aging test is very useful to the manufacturer. Most memory devices support multiple pin selection, so the aging test system reads data back in a cluster. Some systems have a wide data bus. Each cluster can read multiple devices at the same time, and then the devices are divided by computer hosts or similar machines. Increasing the number of parallel signals on the Aging board can increase the speed, reduce the number of devices connected to the same parallel signal line, and reduce the load characteristics of the board and devices.
‧ Volatile memory (DRAM and SRAM)
Volatile memory is the simplest to test, because it can be wiped multiple times without special algorithms or time sequences. Generally, all devices write data at the same time, and then select each device in turn, read back the data and compare it.
Since slow refresh tests can be repeated during aging, DRAM aging tests can save a lot of time for the post-testing process. Refresh test requires that the data be written to the memory first, and then wait for a period of time to discharge defective storage units, and then read back the data from the memory to find defective storage units. Putting this part of the test into aging means that the testing process after aging does not have to perform this kind of time-consuming inspection, thus saving time.
‧ Non-volatile memory (EPROM and EEPROM)
It is difficult to test the non-volatile memory, because the content must be erased before writing, which makes the system algorithm more difficult. Special voltages must also be used for erasure. However, the test method is basically the same: write data into the memory and read it back using more complex algorithms.
Aging Testing System Performance
There are many factors that will affect the overall performance of the aging testing system. The following are some main aspects:
1. First, select the test method.
Ideally, the device spends the least time on the aging process, which can increase the overall output. Poor electrical performance conditions help to accelerate the occurrence of faults. Therefore, systems that can perform repeated tests quickly can reduce the overall aging time. The more internal node switches per unit of time, the more devices are tested, and the faster the fault occurs.
2. complexity of aging board interconnectivity, PCB design and bias circuit.
The aging testing system may be called high-speed testing by some people. However, if the mechanical connection or the characteristics of the aging board weaken the signal quality, the testing speed will be a problem. For example, too many mechanical and electrical connections will increase the total capacitance and inductance of the entire system, poor design of the aging board will produce noise and Crosstalk, and poor pin drive design will make the fast signal along the required driver the current size is limited, etc, these are only the bottlenecks that affect the speed. In addition, the aging performance is also affected due to the excessive load and the selection of impedance, circuit bias, and protection component value.
3. Computer interfaces and data collection methods.
Some aging testing systems adopt the partitioning method. One data collection host controls multiple aging boards, and some systems adopt board-based acquisition. From the actual situation, the single board method can collect more data, and may have a larger test output.
4. Download and convert the high-speed tester program.
Some aging testing systems have their own testing languages and do not need to develop programs for tested devices that require 100% node switching. Some systems can directly convert high-speed tester programs to aging applications, more accurate tests can be performed during the aging process.

5. The system provides the parameter testing capability.
If the aging testing system can perform some speed tests, it can also obtain other relevant failure data for Reliability Research, which also helps to streamline the post-aging testing process.
6. dynamically change the testing parameters based on time, such as voltage and frequency.
If the aging test system can change parameters in real time, it can accelerate the occurrence of faults in the later stages of product life. For some device structures, DC voltage bias and power changes of dynamic signals can accelerate the emergence of advanced life failures.
7. Communication between the computer host and the test system.
Due to the long functional testing procedures, the design of the testing hardware should be as fast as possible. Some systems use slow serial communication, such as RS-232C or similar protocols, while others use bidirectional parallel bus systems, greatly improving the data flow rate.
Conclusion
Testing during aging brings about some cost problems, but the most difficult thing is to find a testing method to complete all possible testing items of the device.
For logical products, the JTAG method is the most common aging testing method, because the test ports on the devices are consistent, so that the aging hardware lines can remain unchanged.
For memory, in small batches, it is better to have a testing system that can process both volatile and non-volatile memory; in large batches, it is better to use different systems to reduce costs.