Analysis of Channel/rank/bank in memory
Recently in the network card to see some of the underlying drivers, the memory bank
, these terms to get around rank
, the Internet to channel
memory
Check some information, said not comprehensive. Here, let's take a step-by-step solution to memory
the mystery, from architecture to reading and writing.
Play Sex
memory
Divided into two kinds,
SRAM
And
DRAM
RAM(Random Access Memory)
Random access memory is called "Random access" because it is relative to the earlier existing storage medium (tape? Long ago), because tape access is linear (remember fast-forward/rewind that), the access time is determined by the distance between the current tape position and the destination (similar to the linear table in the data structure). Need to rotate the head to the proper position, so the longer the distance, the longer the rotation, read and write time is longer. And the great RAM
without this restriction, access time is fixed value (like array such as the following table-type access, subscript is the address), not because the storage data in memory
the location of the impact on the read time.
RAM
Can be broadly divided into two types: SRAM
and DRAM
, the basic principle of the same place, is to store the charge inside the memory, thus for different charges stored 0 or 1. SRAM(Static Random Access Memory)
Static random storage memory and DRAM(Dynamic Random Access Memory)
There are several differences: SRAM
the structure is more complex, the capacity of the unit area is small, access speed quickly; DRAM
The structure is simple, the unit area storage capacity is more, the access time is relatively SRAM
slow, and because the structure is relatively DRAM
simple, The stored charge benefits gradually disappear over time, so a regular recharge ( Refresh
) is required to keep the capacitance stored in the data.
From the diagram SRAM
and the DRAM
structure can be known that the SRAM
use of positive and negative transistor + capacitor ( flip-flop
) construction memory, DRAM
is the use of capacitive storage (MD, these two graphs look good familiar, is to see not understand early forgotten, to cry without tears). Because SRAM
DRAM
of the various characteristics and different, it is SRAM
more suitable as a scratchpad, with CPU fast access to use. DRAM
is suitable for use as the primary memory.
Volatile memory and non-volatile memory
Volatile Memory
the difference between volatile memory () and non-volatile memory ( Non-Volatile Memory
) is whether data stored internally can be saved after a power outage. Volatile memory data will disappear with the loss of power supply, while non-volatile memory can still hold internal data.
Memory Subsystem
DRAM
Because of its simple construction and high density, it is very suitable as the main memory inside the computer. However, since main memory is usually placed CPU
outside, the particles from the factory need to be encapsulated and combined before they can be CPU
connected, so from CPU
the grain to the DRAM
particles in order from large to small channel > DIMM > rank > chip > bank > row/column
. (and LZ before the same, like the first street, which cell unit, which building, several layers of the address pattern of several units). Below, let's take one by one to illustrate these parts:
The structure of the memory (from top to bottom, from big to small)
The correspondence between the memory from the channel to the chip. In particular, it is important to note that rank and memory are not necessarily related to the surface, although the picture is so painted, but do not mislead everyone, is to indicate, the following will be described in detail.
Chip is split down into bank
Bank further down is a storage unit, horizontal row
, vertical column column
, each row column
below has a row buffer
, used to temporarily read out a row
row of data. (is not very simple, is not very similar to the pattern of your home community?) yeah! So easy ~)
Functional block diagram within a single dram particle (image from Micron)
channel
And
DIMM
After coming out of the memory controller, the first thing to arrive is channel
that each channel
one needs a set of memory controllers, 2 channel
two ... And so on And each channel
can have a lot of DIMM(Dual In-line Memory Module)
groups, DIMM
is currently able to buy in the consumer market, you can usually see the memory module. Because n years ago the motherboard had to buy memory particles (chip) himself plugged in on the motherboard (think about why the master was so powerful at that time, this composition principle in practice has been exercised), and then developed SIMM (Single In-line Memory Module)
, will be a number of memory particles ( chip
) welded to a circuit board, become memory module, Insert the secondary circuit board on the motherboard. Next, in order to increase the throughput, the width of a memory module from SIMM
32bit to DIMM
64bit, this design has been used so far.
From the era of memory particles, SIMM
there have been reverse telecommuting to weld the memory particles to the SIMM
circuit board, because the memory is very expensive, so a little bit of money can be used to replace the memory particles on the new computer.
rank
And
chip
rank
Refers to cs(Chip Select,片选)
all memory particles connected to the same chips, the memory controller can read and write to rank
all the same chips simultaneously, and rank
share the chip
same control signal in the same. The current computer, because a set of channel width is 64bit, so can read and write 8byte data, if it is a ECC
function of memory controller and ECC
memory module, then a set of channel's bit width is 72bit.
Rank1 and Rank2 share the same set of addr/command
signal lines, using the CS slice selection line to select the group to read or write, and then send the storage content via the MUX
multiplexer.
Many people have the wrong understanding, often in chip
the number or in the memory module of the single/double face rank
to judge, but in fact should be the memory controller and the size of the memory particles to judge. At present, the majority of the memory controller channel of home PC is 64bit wide, and the bit width of memory particle is 8bit. So 8 particles can meet the needs of the memory controller, which is a group rank
. But occasionally there are memory modules made of 16bit-bit-wide memory particles, at which time 4 particle chip is a group rank
.
This requires special attention when using motherboards with the Intel H61/H81 chipset and traditional single channel, because Intel restricts h64/h81 to support only 2 groups per channel, rank
rather than 4 groups rank
, Some motherboards each channel also made 2 sets of memory module slots, causing some users of the same group channel into 2 memory modules (memory bar) can recognize the full memory capacity (for double-sided single rank
memory module is so), but some users can only recognize half of the capacity (double rank
memory Module).
bank
,
row
,
column
bank
Further down is the actual storage unit element of the circuit, in general, the horizontal selection of the line is called row(row enable, row select, word line)
, the longitudinal signal transmission line is called column(bitline)
, each group bank
below will also have a row buffer(sense amplifer)
, responsible for the read out of the content of the row
temporary, waiting column
The correct bits are output after the address is sent, and the stored content is determined to be 0 or 1.
A bank's read operation.
A write operation for a bank.
How to read and write memory
Indicates the memory read and write mode, the first memory controller will transmit 1 sets of addresses to the memory, the controller then transmits the control signal, if it is more rank
, CS
it will be sent to the target of the corresponding signal selection rank
. Then, since each is composed of rank
multiple chip
components, each chip
only responsible for a portion of the data read, chip
receive the address signal, the address into the internal row/column
decoder to find the corresponding bank
address (each manufacturer of bank
each product internal The combination may be different, so the corresponding will be slightly different), and then open the row
line, the same row row
of internal content will flow to the row buffer
inside, row buffer
judging the signal is 0 or 1 after the output of the storage content.
In addition to the address data, the writing will be sent to the inside of the chip input buffer
, as well as the row/column
decoder to find the corresponding address after the write.
Line relationship between the memory controller and the DIMM
The more the better, the faster the reading and writing ability
Home computer Memory controller has entered the dual-channel memory controller for many years, the acceleration principle is to increase the bit width, the ability to read and write more data simultaneously.
Another way to increase the bandwidth is to reduce latency, use multiple, chip
or bank
achieve. General memory read delay for command release + memory read delay + output content, if the command release delay of 2NS, memory read latency is 10ns, output content delay is 2ns, then read two data delay is (2+10+2) x2 = 28ns.
If the data can be split into 2 memory particles, then the two read latencies will be reduced to 2+2+10+2=16ns, because there is no need to wait until the reading of the previous data is completed before issuing the next read command, which can be emitted when the first data enters the memory read. This concept can also be applied to the current SSD, a large number of high- ce
speed memory chip packaging, usually relatively small ce
package of chips came fast.
It can be known from the time series diagram that this kind of separation of memory space as far as possible, can greatly reduce the delay.
Analysis of Channel/rank/bank in memory