Analysis of PLL initialization code in BootLoader

PLL and CLK Classification

By default, the operating frequency of the S3C2410 CPU is 12 MHz. The PLL circuit can generate a higher clock speed for the CPU and peripheral devices.

The S3C2410 has two PLL: MPLL and UPLL, which are dedicated to UPLL and USB devices. MPLL is used for CPU and other peripheral devices.

MPLL generates three clock frequencies: FCLK, HCLK, and PLCK.

FCLK is used for CPU cores, HCLK is used for AHB Bus devices (such as SDRAM), and PCLK is used for APB bus devices (such as UART ).

You can view the hardware that uses different clock frequencies from the clock structure.

 

MPLL

The following is the MPLL startup process:

 

 

 

Follow the FCLK image to learn about the startup process:

1. After several milliseconds of power-on, the crystal oscillator output is stable. FCLK = crystal oscillator frequency. After the nRESET signal is restored to a high level, the CPU starts to execute commands.

2. We can start MPLL at the beginning of the program. After setting several MPLL registers, it takes some Time (Lock Time) for MPLL output to be stable. During this period of Time (Lock Time), the FCLK is stopped and the CPU is stopped. The length of Lock Time is set by the register LOCKTIME.

3. After the Lock Time, the MPLL output is normal and the CPU is working under the new FCLK.

 

MPLL settings

Setting the clock frequency of S3c2410 is to set the MPLL registers:

1. LOCKTIME: Set to 0x00ffffff

As mentioned above, after mpll is started, it takes a period of time (lock time) to make its output stable. Bit [] is used for upll, and bit [] is used for mpll. Use the saved value 0x00ffffff.

2. fclk settings:

Mpllcon is set to (0x5c <12) | (0x04 <4) | (0x00), and the output frequency is 200 MHz.

Among them, mdiv = 0x5c, pdiv = 0x04, sdiv = 0x00.

Formula mpll (fclk) = (m × fin)/(p × (2 ^ s ))

[M = mdiv + 8, P = pdiv + 2, s = sdiv]

3. clkdivn: used to set the ratio of fclk: hclk: pclk. The default value is.

Here the value is set to 0x03, that is, fclk: hclk: pclk =.

Different clkdivn settings and corresponding clock proportions are as follows:

UPLL settings

Similar to mpll settings. Upllcon is set to (0x48 <12) | (0x03 <4) | (0x02), that is, 48032. The output frequency is 48 MHz.

 

Specific procedures:

Assembly:

1 <br/>; To reduce PLL lock time, adjust the LOCKTIME register. <br/> ldr r0, = LOCKTIME <br/> ldr r1, = 0 xffffff <br/> str r1, [r0] <br/>; delay <br/> mov r0, # DELAY <br/> 5 subs r0, r0, #1 <br/> bne % B5 </p> <p>; configure MPLL <br/> ldr r0, = MPLLCON <br/> ldr r1, = (0x5c <12) + (0x4 <4) + 0x0); Fin = 12 MHz, Fout = 200 MHz <br/> str r1, [r0] <br/>; delay <br/> mov r0, # DELAY <br/> 5 subs r0, r0, #1 <br/> bne % B5 </p> <p>; Configure UPLL <br/> ldr r0, = UPLLCON <br/> ldr r1, = (0x48 <12) + (0x3 <4) + 0x2); Fin = 12 MHz, fout = 48 MHz <br/> str r1, [r0] <br/>; delay <br/> mov r0, #0x200 <br/> 5 subs r0, r0, #1 <br/> bne % B5

C:

# Define FCLK_SPEED 1 </p> <p> # define M_MDIV 0x5C <br/> # define M_PDIV 0x4 <br/> # define M_SDIV 0x0 </p> <p> # define U_M_MDIV 0x48 <br/> # define U_M_PDIV 0x3 <br/> # define U_M_SDIV 0x2 </p> <p> static inline void delay (unsigned long loops) <br/> {<br/> _ asm _ volatile ("1:/n" <br/> "subs % 0, % 1, #1/n "<br/>" bne 1b ":" = r "(loops):" 0 "(loops )); <br/>}</p> <p> int board_init (void) <br/>{< br/> DECLARE_GLOBAL_DATA_PTR; <br/> S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER (); <br/> S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO (); </p> <p>/* to reduce PLL lock time, adjust the LOCKTIME register */<br/> clk_power-> LOCKTIME = 0 xFFFFFF; </p> <p>/* configure MPLL */<br/> clk_power-> MPLLCON = (M_MDIV <12) + (M_PDIV <4) + M_SDIV ); </p> <p>/* some delay between MPLL and UPLL */<br/> delay (4000 ); </p> <p>/* configure UPLL */<br/> clk_power-> UPLLCON = (U_M_MDIV <12) + (U_M_PDIV <4) + U_M_SDIV ); </p> <p>/* some delay between MPLL and UPLL */<br/> delay (8000) <br/>}