Analysis of Setup/hold electrical characteristics from the internal structure angle of the D trigger

is the logical structure diagram of D flip-flop implemented with non-gate, CP is the clock signal input, S and R are both set and clear 0 signal, low effective; D is the signal input terminal, Q signal output terminal;

Let's talk about the principle of D-trigger implementation: (assuming both S and r signals are high, do not place and clear 0 operation)
Cp=0: G3 and G4 closed, Q3 and Q4 output as ' 1 '. Then G5 and G6 Open, q5=d,q6=/d. Q5,q6
The signal changes with the change of the input signal D; G1 and G2 form an SR latch, and we know that when
When the SR latch s and r inputs are high, the latch output remains the same, so Q and/q
Not change.
CP changes from 0 to 1 o'clock: G3 and G4 Open, Q3=q6=/d,q4=q5=d. Characteristics of the SR latch, Q=Q3=D,/Q=/D;
Cp=1: No matter how d changes, Q3 and Q4 signal will not change, so the output will not change, the specific reason from the interest can be pushed;
Here is another time to repeat the cp=0.

From the above analysis, it can be known that the input signal D is at the moment of cp=0, after the delay with the G5 and G6 two and the non-gate TSU before transmission to the Q5 and Q6 end, and then the CP jump to 1 is locked to the output end.
We assume that if the D input signal changes before the CP jumps to 1 4ns (<5ns), then when the CP jumps to 1 o'clock, the input signal D is not transmitted to the Q5 and Q6,SR latch latches will be the data before D changes. In other words, the D input signal is only ready in the >tsu time before the CP jump, and the trigger can latch the data to the Q output port, which is what is said to guarantee the signal settling time.

After the CP jumps to 1, the Q5 and Q6 signals are routed through G3 and G4 two and non-gate delay (THD) to Q3 and Q4, blocking the D input before the SR latch, ensuring that the input data changes in the cp=1 are notaffects the latched result.
We assume that if the D input signal jumps within 5ns after the CP jumps to 1, the Q3 and Q4 have not changed, all are ' 1 ', and the status of Q5 and Q6 will change.   At the time of Cp=1, Q3 and Q4 Follow the change of Q5 and Q6, and the output Q of the end SR latch also jumps, resulting in incorrect output. That is, in the THD time after the CP jump becomes 1, the D signal cannot be changed, that is to say, to guarantee the signal's hold Time (THD).

Analysis of Setup/hold electrical characteristics from the internal structure angle of the D trigger