Analysis of utmi and USB 2.0 PHY high-speed transmission characteristics

 

 

1. Overview

USB2.0 uses the shortening of transmission time series (microframe 125us) and related transmission technologies to increase the overall transmission speed from 12 Mbps to 480 Mbps, increasing the bandwidth by 40 times, it provides conditions for the development of high-bandwidth USB interface products. USB2.0 supports full speed and low speed working environments of USB1.1. Its electrical properties are described in other documents [6]. this section describes the electrical characteristics of high-speed equipment of USB2.0 and related utmi interface specifications. Utmi is called USB2.0 transceiver macrocell interface. This protocol is defined based on the signal characteristics of USB2.0. It can be divided into eight-bit or 16-bit data interfaces. The purpose is to reduce the workload of developers, shorten the product design cycle, and reduce risks. This interface module is mainly used to process the USB protocol and signal at the underlying physical layer. It can be integrated with SIE to form a dedicated ASIC chip or independently used as the PHY transceiver chip, the following uses an 8-bit interface as an example to describe the operating principle and design features of Phy.

2. Main functions and principles of utmi

First, to ensure compatibility, phy should support full speed and high speed working modes. For this high-speed hub (root hub or hub)

You must be able to check whether the device is a high-speed port or a full-speed port for the corresponding speed mode. Therefore, the signal interface must implement the following functions:

L dynamic transmission between interfaces at different rates

L High-Speed Device Detection)

L high-speed device disconnection detection (hs_disconnect)

L ability to transmit high-speed/full-speed differential signals (impedance matching required)

L send and detect high-speed packet start signals (Sync)

L send and detect high-speed packet end signals (EOP)

L nrzi encoding and bit filling (bit stuff/bit unstuff)

L support pending and resetting operations

Figure 1 functional module of USB2.0 PHY

Figure 1 describes the utmi functional modules. The operating principle is as follows, first, the high-speed device connection detection (HS detection handshake) (later described in detail), after the detection is completed, switch to the corresponding working mode, and then wait for the host and device to transmit data streams. When the receiver detects the signal sent from the host to the device on the USB data cable D + and D-, it first restores the signal and obtains the correct synchronous signal before sending it to the buffer zone, after nrzi decoding and bit anti-filling, the serial signal is converted into a parallel signal and finally sent to the device sie for processing. When the sie on the device needs to send data packets, utmi transmits the compiled nrzi serial data streams to the host through the transmitter in reverse order. To reduce power consumption, utmi supports the suspension function. Its working status is 2.

Figure 2 utmi Workflow

3. Analysis of each function module

3.1 clock Multiplier

This module generates the UTM internal clock and provides an external clock CLK output to sie. The Protocol requires that the clock frequency error range be less than 10% (± 6 MHz ), the accuracy of the clock output CLK is ± 500ppm (30.0 kHz), and a stable clock frequency is required within Ms.

For an 8-bit data interface, the output of the external clock CLK is 60 MHz. In a high-speed environment, an external clock CLK cycle is the time required for high-speed devices to transmit a byte of data, that is, () MS/per byte; while in a high-speed environment, the five external clock CLK cycles are the time required to transmit a bit of data at full speed, that is, () MS/per bit, so, typically, the transmission speed of one byte data is 40 external CLK cycles. If a bit is filled, 45 cycles are required.

2.2 sending and Receiver

This article focuses on the features of high-speed transmission. In a high-speed environment, the USB transmission rate is 480 Mbps. This value can be used, on the one hand, to use existing cables and connectors, and on the other hand, through extensive research and testing of semiconductor technology, this speed is not only correct in the production process, but also fully compatible with USB 1.1. To reduce the impact of noise and power supply jitter on transmission and improve transmission speed, select the differential current mode drive.

One of the biggest challenges of USB2.0 is to design a high-performance Transceiver with low output impedance [7]. During transmission at Mbps, if the path does not end according to the performance requirement, reflection will occur. Therefore, when transmitting high-speed signals, a 90Ω resistor must be matched to the cable to eliminate signal reflection, and the current source can also increase noise resistance when driving this low output impedance. When the High-speed drive is working, the bus is idle, and both data lines are in the low status, in this case, the full speed drive of the hub and the full speed drive of the device are functionally equivalent to a 45Ω resistor (as shown in the 3 circle). The difference resistance of 90Ω is synthesized to produce a zero coefficient reflection. The Protocol specifies that the output impedance of the full-speed drive is 45 Ω ± 10% to meet the needs of the high-speed transceiver.

High-speed data transmission is the same as low-speed/full-speed data transmission. Data streams are encoded based on non-zero code and are transmitted as differential signals on the cable. The high-speed signal is sent by the high-speed current drive. Based on the corresponding J or K signal in the high-speed environment, the drive transmits the current to the D + and D-data lines to 78mA current respectively, through a 22.5 Ω load (two 45Ω loads are connected in parallel), a voltage similar to ± 400mv is generated on the D + and D-signal lines to achieve high-speed differential transmission.

Figure 3 basic components of High-speed differential signal Transceiver

2.2 hs dll and FS DLL

This module contains a delayed phase-locked loop, which can be DLL or PLL. Its main function is to extract high-speed or full-speed data streams and recover the clock to synchronize and correctly extract data. It can be concluded that this module is the core module in utmi, and its performance determines the correctness of the data received by utmi. For more information, see [8].

. 3.3 MUX/Demux

Select full speed or high-speed data streams.

3.4 nrzi encoding/Decoding

The principle is the same as that of USB1.1 to improve the signal's anti-noise capability. As shown in 4, nrzi is a differential non-zero encoding, which is different from the conventional non-zero encoding (NRZ) the difference between code encoding is that each "0" code has a jump, and each "1" Code does not. In nrzi encoding, the signal is decoded through the jump of the polarity of the adjacent code element, rather than simply taking the absolute level as the standard, so as to obtain a higher anti-interference capability.

Figure 4 nrzi encoding method

3.5 bit stuff/bit unstuff

The nrzi encoding method may encounter a serious problem, that is, if a long string of continuous "1" will cause a non-level hop and gradual accumulation, causing the machine to collapse and eventually lose the synchronization signal, serious errors occur in the read sequence. Therefore, between nrzi encoding, bit-filling is also required. In the continuous transmission of 6 "1" bits, force to add a hop in the nrzi-encoded data stream. This ensures that the receiver can detect a hop at least every seven digits at a time interval to keep the receiver synchronized with the transmitted data. Figure 5 illustrates how bit filling works.

Figure 5 filling modes

The bit filling operation starts from synchronizing data segments (as shown in Figure 7) throughout the entire transfer process and strictly complies with the bit filling rules, we can also see that the end EOF the high-speed package also uses the bit filling rule to prompt the end of the packet.

3.6 serial/parallel conversion

Use the RX shift/hold registers or the Tx shift/hold registers to convert the received data or the data to be sent in a serial or parallel manner.

3.7 basic control unit

The basic control unit is to control the utmi working status and check whether the received data is valid. Here we will mainly introduce the emission envelope detector (squelch ).

In a low-voltage signal environment, in order to avoid noise signals caused by cables as signals to be transmitted, the emission envelope detector (squelch) must be used to check whether the signals on the bus are effective. When the bus is idle, the high-speed differential receiver is in the static noise state. When the packet start signal is detected, the high-speed differential receiver is activated. When the differential signal level is less than 100mV, the detector indicates that the signal on the bus is invalid. Only when the signal level is greater than 150mV, the detector indicates that the received high-speed differential message is valid. However, this method may also lead to synchronization latency, that is, a maximum of four latencies may occur between the detected envelope and the start receiver, however, this latency does not cause synchronization problems [3].

4. Analysis of other functions

4.1 high-speed device connection detection (HS detection handshake)

As mentioned above, the connection detection (HS detection handshake) of high-speed devices must be performed after the device is connected, suspended for recovery, or reset ). Connection detection of high-speed devices was initially carried out in a full-speed signal environment. A handshake signal is sent between a high-speed device and a high-speed hub to indicate whether the device is a high-speed device.

If the handshake signal fails to be transmitted, the default value is full-speed device.

When the device is connected to the Hub hub or host, the full speed and high speed devices have a kb pull-up resistor on the D + line, because the drop-down resistor is 15 kb Ω, d + is added to the DC level of approximately 90%. When the hub detects the D + high level, it is considered to be connected to the full-speed device. In this case, the software sends a reset signal to the hub through the reset command, so that the hub drives a se0 signal (both D + and D-are low) for more than 10 ms. After the high-speed device detects the reset signal, it sends a chirp K signal to the Hub (1 ~ 7 ms ). If the High-Speed receiver of the hub detects the Chirk signal within 2.5 microseconds after the device sends the Chirk signal, it returns an alternate Chirk and chirj signal sequence. The device detects these 6 Linear Frequency Modulation pulse chirp sequences (three alternate kJ signal pairs ),

The Hub places the connection port in the high-speed enabling status, and pulls the resistance from D + to enable the High-Speed Device terminal, and sets the high-speed device default status.

If the device does not send a Chirk signal after the reset, or the device does not detect the alternate kJ signal sequence of the hub response, the high-speed device continues to operate in full-speed mode. The event timing diagram in Figure 6 illustrates the connection Process of High-Speed devices.

Figure 6 sequence chart of the hs_detection_handshake event

The T0 time indicates that hs handshake starts. At time t1, the device sends the Chirk signal and ends at time t2. The downstream port sends the KJ alternating pulse sequence at time t3. If the device receives the chirp signal from the downstream port at time T6, the device disconnects the Pulling Resistance of D + at the time of T7, and sets it to the HS terminal and the HS default status, waiting for the end of the high-speed connection detection. T8 indicates the time when the bus stops the downstream port and sends the chirp kJ signal. T9 indicates the time when the bus high-speed connection detection is terminated or after the D + pull-up resistance is disconnected, sets the latest working state for the HS terminal to enter the HS by default.

4.2 high-speed device disconnection detection (hs_disconnect)

Because the connection of High-Speed devices does not increase the voltage, the hub must use different methods to detect device removal. When a high-speed device is idle, the D + and D-data lines remain low. when the device is disconnected, no obvious changes are detected online, but the differential terminal resistance of the device disappears, the high-speed packages continue to be transmitted from the port connected to the original device. When the package reaches the load-Free Path endpoint, a large reflection will return to the Hub interface, doubling the differential voltage of the Hub Connection port, when the hub detects this double voltage, it indicates that the device has been removed. Protocol definition: hs_disconnect is generally used to test the differential level of the hub after the extended end of the high-speed packet, hseop, if the value is greater than or equal to 625mV, the device is disconnected. 4.3 High-Speed Packet start and synchronization sequence (Sync)

Because the device and the host do not share the same clock, the receiving device cannot correctly know when the transmission device will send a new information package. To synchronize transmission and receipt, each information package requires a sync as the package to synchronize the pulse of the receiving device with the transmitted data. In a high-speed environment, sync is a 32-bit: 15 alternate duplicate kJ signal pairs, and finally two K signals. Figure 7 shows the high-speed synchronization sequence and package start character.

Figure 7 high-speed sync Information Package

4.4 express package terminator (EOP)

Principle 8 shows how the high-speed package Terminator detects. Each package ends with an EOP sequence. Except that the extended end of High-Speed Packet (hseop) in the high-speed frame start packet is 40 bits, the end of other high-speed packets is 8 bits. The 8-bit Terminator is an encoding of the 01111111b nrzi with no padding. If the first digit is J, the end character of the high-speed information package is kkkkkkk. If the first digit is K, the end of the high-speed information package is jjjjjjjj. In any case, the transmitted 7-bit sequence will cause a bit fill error, that is, the receiver detects an intentional fill error sequence and knows that the packet ends, even if this is not an EOP, but there is a real bit Filling error, which is no exception.

8 high-speed transmission packet Terminator Detection

4.5 reset and suspend

Both the reset and suspension signals of the device send an idle bus signal greater than 3 ms. At the same time, both high-speed devices are switched to the full-speed signal environment in both statuses, therefore, high-speed devices must be able to distinguish between the two events. When the High-Speed Device disconnects the high-speed resistor and reconnects the 1.5 K upstream resistor to the full-speed mode, within ms to Ms, the bus detects the status of the D + and D-data lines to determine whether the bus enters the reset or suspension status. If both D + and D-are low, that is, single-ended 0, the bus is resetting. If D + is high (UP) and D-is low (down ), the bus sends an idle signal at full speed, indicating that the device is suspended.

5. Conclusion

This article analyzes the features of the high-speed transmission environment of the USB2.0 interface and the working principle of the 8-bit phy in this mode. To ensure that USB2.0 works properly in high-speed and full-speed environments, the utmi protocol is also analyzed. The article also makes a detailed analysis on the differential nrzi encoding of USB transmission and how to enhance the anti-noise capability and ensure the correctness of data. This thesis has good reference value for utmi and USB2.0 interface design.