Application of DSP in synchronous AC sampling of Power System

Application of DSP in synchronous AC sampling of Power System

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With the rapid development of China's power industry, the power system has higher requirements for the collection of power generation, transmission, distribution, and consumption. As a prerequisite for real-time control, monitoring, and scheduling automation of the power system, electric power collection has undoubtedly played an important role. However, in the electric power collection process, due to harmonic and other interference factors, how to accurately and quickly collect various analog quantities in the power system has been a hot topic in Power System Research [1].

Depending on the sampling signal, sampling can be divided into two categories: DC sampling and AC sampling. The DC Sampling algorithm is simple and easy to filter. However, the maintenance is complicated, the delay is long, and real-time signal collection cannot be implemented. Therefore, the Application in Power Systems is increasingly limited. Good real-time communication sampling, low phase distortion, low investment, and easy maintenance. The disadvantage is that the algorithm is complex and the/D conversion speed and CPU processing speed are high [2]. With the development of microcomputer technology, AC sampling gradually replaces DC sampling. In recent years, the performance of various integrated single-chip DSPs has been greatly improved, and the price has been greatly reduced. More and more single-chip microcomputer users are choosing DSP devices to improve product performance. This paper takes TI's new 2000 series DSP () as an example to discuss the application of DSP in AC sampling of power system.

1. Overall Design

In addition to the voltage and current at the stator end of the generator, the excitation voltage, excitation current, and bus voltage of the excitation device should also be taken into account. To improve reliability, when the second group of instruments PT is added, the number of analog channels to be collected will increase to 12. Therefore, we need to weigh the sampling accuracy, speed, and economic cost among other aspects, select an appropriate sampling method and sampling frequency, and pay attention to the isolation of strong and weak current and electromagnetic interference, to determine the final software and hardware design and component selection. See [4] for detailed analysis of factors affecting the software synchronous sampling accuracy and hardware synchronous sampling accuracy and improvement measures. The system sampling module uses the hardware synchronous sampling method and directly controls the sampling holding circuit through the hardware Phase-Locked Loop synchronization to achieve higher synchronization accuracy. In order for the sampled signal f * (t) to reflect the sampled analog signal f (t), the sampling frequency must satisfy the sampling theorem, that is, the sampling frequency fs must be twice the maximum effective harmonic frequency fmax contained in the analog quantity. In actual sampling, the fs is usually ≥10 fmax to ensure that the sampling signal can accurately represent the analog signal to be sampled. When the sampling frequency is too high, it will increase the burden on the processor and affect real-time performance. The initial design of this system is set to 40 points, that is, the sampling frequency is about 2 kHz.

Figure 1 Structure of the AC sampling module

2. Hardware Design of the sampling system

The hardware structure 1 of the AC sampling module shows that it includes the isolation conversion circuit, channel selection circuit, limit circuit, synchronous square wave conversion circuit, mode/number conversion and control circuit.

In the isolated conversion circuit, the hall sensor with magnetic compensation is used to convert the voltage and current signals sent by PT and CT to the weak current voltage signals allowed by the/D channel of the same waveform. The channel selection circuit uses two 2-choose-1 analog multiplexing selector MC14053B to select different A and B groups through different addressing, and samples the six-channel analog quantity at the same time. The two circuits are relatively simple and will not be described in detail.

2.1 limit circuit

In the mode/number conversion, if the/D converter is damaged, the detection and control functions cannot be implemented. For security reasons, the/D Converter adopts A limiting circuit to ensure the security of the system A/D converter. Traditional Limited-width devices, such as the Zener diode Limited-width device, the regulator reverse limiter, and the bridge-type Limited-width device, all use the broken-down characteristics of the diode. In the breakdown area, the internal resistance of the diode is not zero and there is a leakage current, so the voltage value is not constant and not easy to adjust. As shown in limit circuit 2 designed by the system, set UR = ± 2. 5 V, and the TL431 provides high-precision reference level.

Figure 2 bidirectional Limiting Circuit

2.2 synchronous square wave transform circuit and Frequency Sampling

In order to ensure the Sampling Accuracy of the excitation device, the sampling frequency must be quickly adaptive, and the frequency change of power on the machine side must be tracked synchronously. As shown in figure 3, the designed synchronous square wave switching circuit consists of the lagging voltage comparison circuit, high-speed optical coupling circuit, phase-locking frequency doubling circuit and pulse shaping circuit. A hysteresis comparison circuit consisting of U1A (1/4 of LM339) and Q1 (9012) changes the input signal of a sine wave to 0 ~ 5 V of the same frequency square wave signal, and the use of voltage delay characteristics to eliminate the input signal jitter at zero point may occur. The high-speed optical coupling 6n133 isolates the analog part and the digital part of the circuit, and further isolates the electrical connection between strong and weak current. The Phase-lock frequency doubling circuit consists of the Phase-Locked Loop Circuit U2 (CD4046) and the decimal frequency division circuit CD4017. The frequency is calculated based on the 40-point sampling every week, and the 40-point division is completed based on two cd4017s. Due to the negative phase feedback of the Phase-Locked Loop, when the phase-locked loop is locked (D5 is the lock indicator), the output signal of U6_7 is synchronized with the input signal of U2_14, that is, it is synchronized with the sine input signal, at this time, the output signal frequency of U2_4 is 40 times of the sine signal frequency and follows its synchronous change.

The synchronous signal output by U6_7 is sent to the capture module CAP1 of 2017121.for frequency measurement to meet the requirements of the subsequent power system stabilizer (PSS) in excitation control) and V/F restrictions. The synchronous frequency doubling signal output by U2_4 is shaped by the CD4528 pulse width to obtain A suitable pulse signal, which is used as the trigger signal for A/D sampling persistence. This sampling module uses hardware Phase Lock synchronization to avoid the uncertainty of the interrupt response time in Software Synchronization and achieve higher synchronization accuracy. To change the number of sampling points per week, you only need to change the connections reset by the CD4017 pin.

Figure 3 synchronous Square Wave Transformation and Phase-Locked Loop Frequency Doubling Circuit

2.3 mode/number conversion and Control Circuit

There is A 12-bit A/D converter with A 25 MHz conversion frequency. The front end of the 12-bit A/D converter is two 8-way switches and two-way simultaneous sampling/holding devices, when the requirements are not very high, you can use it to form a synchronous sequential sampling circuit, or add an external sampling holder to form synchronous sampling. Considering the importance of electric power detection of the generator excitation control device and its high requirement on electric power acquisition accuracy and speed, the system sampling module selects an external six-channel 16-Bit mode/number converter ADS8364. It includes six high-speed sampling-amplifier, six high-speed ADC, a reference voltage source, and three reference voltage buffers, which can provide a synchronous sampling rate of 250kSPS, converts all six input channels with ultra-low power consumption (69 mW/per channel) to lower the unit cost for all channels [5]. In addition, the data output interface voltage of the six channels is between 2.7V and 5.5V, which facilitates direct interface with DSP and saves intermediate level conversion. The six completely independent ADCs can greatly improve the overall parallel processing speed of the hardware. At 50 kHz input signal, they can still ensure superior common-mode suppression capability greater than 80 dB, it is particularly suitable for interference environments such as engine control and energy conversion. Figure 4 shows the mode/number conversion and control circuit, the differential input V + IN of each channel of the ADS8364 must convert the bipolar AC signal to 0 ~ through the proportional operation amplifier and the level self-lifting circuit ~ 5 V signal. The maximum clock frequency of the/D converter is 5 MHz, which is provided by the PWM1 port of. The ADD and BYTE bits are set to low. The IOPF0 controls the reset start of the ADS8364 and three-to-six channels) the sampling persistence trigger signal comes from the output signal HOLD of the synchronous multiplier. After each pair of channels are converted, the EOC sends an external interrupt request to XINT1. After the responds to the interrupt request, select the corresponding channel through the address line to read the converted data from the data line.

Figure 4 mode/number conversion and Control Circuit

Figure 5 synchronization sampling software main program flowchart

3 Software Design of sampling system

The software structure of this sampling system is complex and involves many algorithms. To facilitate debugging and maintenance, the software design follows the modular, top-down, and gradually refined programming ideas. The software adopts the mixed programming of C language and assembly language. The main software can be divided into three modules: main program, sampling interrupt service subprogram, and frequency capture interrupt service subprogram. Figure 5 shows the main program flow chart. The software works in the following process: After the system is powered on and reset, it first follows the selected mode (Jump to H0 SRAM mode during debugging, in actual application, it is in the Jump to Flash mode). The bootstrap loader jumps to the main program portal, and initializes related variables, data buffers, control registers, and status registers; call the event manager EV initialization program, set the cycle (5 MHz) and duty cycle of PWM1, capture the input clock frequency and cycle of base T2 when unit CAP1 is set, and start T1 and T2; initialize the peripheral extended interrupt PIE, enable the used external interrupt XINT1 and capture interrupt, clear the interrupt flag, and enable the Global interrupt; then reset and initialize the external ADS8364, wait for the external interrupt, in the interrupt service subroutine, read the data obtained after A/D conversion into the allocated data buffer. After the week wave sampling is completed, the original tunnel Sampling physical quantity (AC, DC) different digital filtering programs are called. After data processing, various calculation subroutines are called to calculate the required valid values, active power, reactive power, power factor, and average value. The flowchart of sampling interrupt subprograms and frequency capture interrupt service subprograms is shown in Figure 6. The baseline accuracy of frequency capture interruption is 0.43 μs. Is a fixed-point DSP. In order to improve the accuracy and speed of operation, the IQmath Library provided by TI is fully used in the software design to achieve seamless interfaces between floating-point operation and fixed-point program code, it simplifies program development and greatly improves the real-time running of programs [6].

(A) flowchart of A/D conversion interruption service subroutine

(B) frequency capture interrupt service subroutine Flowchart

Figure 6

The synchronous sampling module designed in this paper has passed various functional tests and achieved the expected goal. The hardware design and software programming of this scheme can be used as a reference to improve the speed and accuracy of simultaneous acquisition of multi-channel electricity in energy, metallurgy and other industries. The subprograms have good portability and are of reference value for the design of other DSP application systems.