Application of SDRAM in Arbitrary Waveform Generator

Application of SDRAM in Arbitrary Waveform Generator

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Source: Electronic Technology Application Author: Chu Fei Huang Yang Jing Huang

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Arbitrary Waveform generators play an important role in the radar and communication fields. However, most arbitrary waveform generators currently use static memory. This makes it difficult to increase the operating frequency of any waveform generator, and thus cannot accurately express complex signals. The design based on dynamic memory (SDRAM) introduced in this article can effectively solve this problem, and a design method to simplify the SDRAM controller is discussed in detail.

1 overall plan for any Waveform Generator

The operating frequency, resolution, and storage length are the three most critical performance parameters of any waveform generator. High operating frequency means high output signal frequency and bandwidth. High Resolution usually means high signal-to-noise ratio, while the storage length determines the signal accuracy. The solution described below is an arbitrary waveform generator/card (1) developed by the author. The working frequency is 300 MHz, the resolution is 14 bits, and the storage length is 8 m characters, it has been widely used.

 

The circuit has two main states: Write Data status and read data status. The following briefly describes the working process.

Write Data status: the CPU calculates the waveform data based on the designed waveform and converts it to a 14-bit unsigned number. The bus switch is enabled to shield the FIFO operation, the waveform data is alternately written into SDRAM1 and SDRAM2 through the interface circuit, that is, the data stored in SDRAM1 is, 4, 6 ...; store Data 1, 3, 5, 7 in sequence in SDRAM2... (as shown in Table 1 ).

 

Read data status: Enable the FIFO channel and disable the bus switch to disconnect the data connection between the SDRAM and the CPU. under the control of the SDRAM controller, the data in SDRAM1/2 is read in parallel; the data stream is obtained through a FIFO buffer, and then converted to a 16-bit string by 32 bits. After the data rate is increased by 2 times, the DAC is provided for data-mode conversion, the edited signal is displayed.

Figure 1 uses two pieces of SDRAM to work in parallel, because a single piece of SDRAM cannot provide MSPs of data streams. The actual device is a K4S641632C-TC60 with a 166 MHz clock. The output data of the FIFO cache SDRAM is converted into a continuous data stream, so that the normal data output can be maintained when the SDRAM is refreshed. The actual device is two parallel IDT72V263L6PF devices. The write clock is 166 MHz, and the read clock is 150 MHz. The function of parallel string conversion is to increase the data rate, which is completed in the DAC device. The author uses AD9755AST with good dynamic performance. The CPU and control interface is a PC-based ISA device that can be improved to a PCI device. The clock circuit is used to generate a synchronous clock of 166MHz and 150MHz. The following focuses on the design of the SDRAM controller, which is one of the main characteristics of the system.

2 Design of SDRAM Controller

2.1 main features of SDRAM

Compared with static memory (SRAM), SDRAM has a large capacity (usually several to dozens of times). Compared with ddr sdram or RDRAM, its control is relatively simple, therefore, it is still a good choice for large-capacity storage projects. Several important basic concepts described below reflect its main features.

Row and column addresses: the addresses of SDRAM are reused, which effectively reduces the chip pins.

Pre-charging: read/write operations are only valid for pre-charged rows. That is to say, at least one pre-charging operation is required before data read/write operations are performed across rows.

Automatic Refresh: As we all know, as long as it is a dynamic RAM, there will be a refresh problem, and SDRAM is no exception. It is usually necessary to refresh all storage units every 64 ms.

Auto-Refresh: You can set the chip to enter the auto-Refresh status when you need to retain the data in the chip without any operation.

Working Mode register: registers used to control the working mode of SDRAM (as shown in table 2 ).

 

 

2.2 SDRAM Status Process

The complete state machine of SDRAM consists of 17 states, and the state transfer is non-random (2 ). Because of the large number of States and their complex conversion relationships, the control of SDRAM is complicated.

 

It should be noted that the State transfer of SDRAM is divided into automatic transfer and manual transfer (in Figure 2, the width arrow is used to distinguish between them ). Automatic Transfer enters the next state immediately after the current State ends. Manual transfer stops in the current State after the current State ends. Only one command in the current State can enter the next state.

As you can imagine, it is not easy to design such a complex control process. Fortunately, a complete state machine is not required in most applications. The following describes a simplified SDRAM state machine.

2.3 simplified status process

According to the characteristics of any waveform generator, the functions of the SDRAM are simplified as follows:

(1) omitted random access, fixed as sequential read/write;

(2) The standby, auto-Refresh, and common read/write functions are omitted;

(3) omit all pending functions;

(4) The working mode is fixed to burst-type read and single-type write;

(5) Data delay is fixed to three clock periods;

(6) The refresh mode only uses the automatic refresh mode. when the device is idle, it is in the continuous automatic refresh status;

(7) the device is initialized only once after power-on, and the working mode cannot be changed;

(8) The burst mode is fixed as the sequence mode, and the burst length is fixed as the whole page;

(9) only read/write commands with pre-charging are used. After each read/write operation is completed, an automatic refresh cycle is started.

The simplified state machine 3 is shown above.

 

2.4 Implementation of EPLD for SDRAM Controller

In order to realize the preceding simplified SDRAM control function, an EPLD device MAX7256ATC144-6 manufactured by ALTERA was used. Figure 4 shows the SDRAM control flow of any waveform generator. Since the specific programming involves many details, I will not repeat it here. Its main functions are as follows:

(1) interfaces with the CPU through the ISA bus to receive waveform data and read commands;

(2) Automatic initialization upon power-on;

(3) generate a 23-bit (8 M memory space) linear address and output it in the form of row-column multiplexing;

(4) generate the control signal of the SDRAM to complete the read, write, and automatic refresh functions;

(5) control the FIFO to solve the problem that the SDRAM refresh and waveform length are not multiples of the page length.

 

 

Although it is indeed complicated to fully apply the SDRAM, the function can be reasonably simplified based on the principle of "enough, it is completely feasible to design an SDRAM Controller with special requirements and applicable to specific conditions. At present, I have applied the arbitrary waveform generator based on SDRAM to multiple R & D projects.

 

References

1 K4S641632C Data Sheet. Samsung Inc, June 1999.

2 MAX7000A Data Sheet. IDT Inc, October 2000.

3 Song wanjie. CPLD technology and application. Xi'an: Xi'an University of Electronic Science and Technology Press, 2001