ARM Architecture and System Learning (II.)--Level 3 pipeline

ARM Architecture and System Learning (II.)--level 3 pipelineTags: storage embedded assembler C2012-04-18 00:44 5414 People read Comments (4) favorite reports Classification:ARM7 (+)

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See a lot of the Assembly on the return of the program and the return of the processing address are very special, think about the original pipeline effect. So, decided to summarize learning under arm pipeline.

The ARM7 processor uses a Class 3 pipeline to increase the speed of the processor instruction stream, providing 0.9mips/mhz instruction processing speed.

Ps:

MIPS (Million instruction per Second) indicates how many millions instructions per second. 0.9MIPS, for example, represents 900,000 instructions per second.

Mips/mhz indicates how many MIPS the CPU can perform at run per MHz, such as 0.9mips/mhz, if the CPU runs at a frequency of 1MHz and executes 900,000 instructions per second.

If the CPU runs at a frequency of 20MHz, it can run 18 million instructions per second. Mips/mhz can reflect the speed of the CPU very well.

Level 3 pipeline as shown (PC as program counter), Pipelining uses 3 stages, so the instruction is executed in 3 stages.

⑴ refers to loading an instruction from memory

⑵ decoding to identify instructions to be executed

⑶ executes the processing instruction and writes the result to the Register

Previously learned 51 microcontroller, because it is relatively simple, so its processor can only complete one instruction read and execute, will execute the next instruction. This way, the PC always points to an instruction that is "executing".

For ARM7, because it is a 3-level pipeline, the processing of the instructions is divided into 3 stages described above.

So the process is actually like this: arm is executing the 1th instruction while decoding the 2nd instruction and removing the 3rd instruction from the memory.

Therefore, the ARM7 pipeline only when taking the 4th instruction, the 1th instruction is complete execution.

Vivid description of the 3-level pipeline processing mechanism

The following sentence is critical: regardless of the state of the processor, the program counter R15 (PC) always points to the "fetching" instruction, rather than to the "executing" instruction or the "decoding" instruction.

It is customary to use an executing instruction as a reference point, that is, the current 1th instruction.

So, the PC always points to the 3rd instruction,

Or, the PC always points to the address of the currently executing instruction address plus 2 instructions.

When the processor is in arm state, each instruction is 4 bytes, so the PC value is the executing instruction address plus 8 bytes, that is:

PC value = Current program execution position + 8 bytes

When the processor is in a thumb state, each instruction is 2 bytes, so the PC value is the executing instruction address plus 4 bytes, which is:

PC value = Current program execution position + 4 bytes

The following example is a good illustration of this problem.

[Plain]View PlainCopyprint?

1. 0x4000 addpc,pc, #4; the instruction being executed to write the address value pc+4 to the PC
2. 0x4004 ...; Instructions that are being decoded
3. 0x4008 ...; The instruction being taken, pc=0x4008
4. 0x400c ...; pc+4=0x400c

Additional explanation is that according to the above description, the pipeline can only be filled by the command to maximize performance, that is, each clock cycle to complete the execution of an instruction (single-cycle instructions).

If the program jumps, the pipeline will be emptied, which will require several clocks to fill the pipeline again. Therefore, as far as possible, the use of jump instructions can improve the execution efficiency of the program.

The above is a general understanding of the ARM73-level pipeline, reference from the learning arm of the teaching material-"Arm embedded system Basic Tutorial (second edition)".

ARM Architecture and System Learning (II.)--Level 3 pipeline