Arm bare metal development (5) SPI

The following bare metal program is based on gt2440 and the compiler is a arm-linux-gcc-4.4.3.

Program structure: This program only has one SPI. s file.

Program process: first, the power-on Reset enters the reset exception. In the reset exception, call the subroutine to close the watchdog, initialize the system clock, initialize the serial port, and finally call SPI to send data, the data sent by SPI is specified in the program. The data sent by this program is a byte character 'a', And the SPI sends the received data to the serial port, which is displayed on the terminal.

 

SPI. S:

1 // register physical address macro definition 2 # define wtcon 0x53000000 3 4 # define locktime 0x4c000000 5 # define mpllcon limit 6 # define upllcon limit 7 # define clkdivn 0x4c000014 8 # define camdivn limit 9 10 # define ulcon0 0x50000000 11 # define ucon0 0x50000004 12 # define ufcon0 0x50000008 13 # define utrstat0 0x50000010 14 # define utxh0 0x50000020 15 # define urxh0 0x50000024 16 # define ubrdiv0 0x50000028 17 // For UART Io 18 # define gphcon 0x56000070 19 20 # define spicon0 0x59000000 21 # define spsta0 0x59000004 22 # define sppre0 0x5900000c 23 # define sptdat0 x 59000010 24 # define sprdat0 0x59000014 25 // For spi0 Io 26 # define gpecon 0x56000040 27 28 29. global _ start 30 _ start: 31 B reset 32 33 // reset Exception Handling 34 Reset: 35 BL disable_watchdog 36 BL init_clock 37 BL init_uart 38 BL spi_send 39 loop: 40 B loop 41 42 // close the watchdog 43 disable_watchdog: 44 LDR r0, = wtcon 45 Bic R1, R0, #0x20 46 STR R1, [R0] 47 48 mov PC, LR 49 50 51 // initialization clock 52 // fclk = 400 MHz, hclk = 100 MHz, pclk = 50 MHz 53 // uclk = 48 MHz 54 init_clock: 55 LDR r0, = locktime 56 LDR R1, = 0x00ffffff 57 STR R1, [R0] 58 LDR r0, = clkdivn 59 LDR R1, = 0x05 60 STR R1, [R0] 61 // set to asynchronous bus mode (because fclk is not equal to hclk) 62 MRC P15, 0, R1, C1, C0, 0 63 Orr R1, R1, #0xc0000000 64 MCR P15, 0, R1, C1, C0, 0 65 66 LDR r0, = mpllcon 67 LDR R1, = 0x5c011 68 STR R1, [R0] 69 LDR r0, = upllcon 70 LDR R1, = 0x38022 71 STR R1, [R0] 72 73 mov PC, LR 74 75 76 // initialize the serial port 77 init_uart: 78 // IO port is set to serial port function 79 LDR r0, = gphcon 80 LDR R1, = 0xa0 81 STR R1, [R0] 82 // No test Bit, 1 stop bit, 8-Bit Data bit 83 LDR r0, = ulcon0 84 LDR R1, = 0x03 85 STR R1, [R0] 86 // pclk as the clock source (50 MHz) 87 LDR r0, = ucon0 88 LDR R1, = 0x05 89 STR R1, [R0] 90 // 115200bps 91 LDR r0, = ubrdiv0 92 LDR R1, = 0x1a 93 STR R1, [R0] 94 95 mov PC, LR 96 97 spi_send: 98 // set Io to SPI mode 99 LDR r0, = (0x2 <26) | (0x2 <24) | (0x2 <22) 100 LDR R1, = gpecon101 STR r0, [R1] 102 // clock frequency (pclk/2/(249 + 1) 103 LDR r0, = sppre0104 LDR R1, = 0xf9105 STR R1, [R0] 106 // polling mode, host mode, sclk enabled, automatic spam mode 107 LDR r0, = spicon0108 LDR R1, = 0x19109 STR R1, [R0] 110 111 wait_send: 112 // check whether the Status Register has 113 LDR R2, = spsta0114 LDR R1, [R2] 115 LDR R3, = 0x01116 and R3, r1, r3117 CMP R3, #0x01118 BNE wait_send119 // sends a byte 120 LDR r0, = sptdat0121 LDR R1, = 0x41 // character a122 STR R1, [R0] 123 124 wait_read: 125 // check whether the Status Register has 126 LDR R1, [R2] 127 LDR R3, = 0x01128 and R3, R1, r3129 CMP R3, #0x01130 BNE wait_read131 // read the received data to r5132 LDR r0, = sprdat01_ldr R5, [R0] 134 // call the serial port to send the received data to terminal 135 BL aurt_send_one_byte 136 137 mov PC, lr138 139 140 aurt_send_one_byte: 141 wait_se: 142 // read sending status bit 143 LDR r0, = utrstat0 144 LDR R1, [R0] 145 and R1, R1, #0x4146 CMP R1, #0x4147 // if the sending status bit is not 0, the status bit 148 BNE wait_se149 // write the data to be sent 150 LDR R3, = utxh0151 STR R5, [R3] 152 mov PC, LR

Makefile:

1 spi.bin:2     arm-linux-gcc -g -c -o spi.o spi.S3     arm-linux-ld -Ttext 0x00000000 -g spi.o -o spi_elf4     arm-linux-objcopy -O binary -S spi_elf spi.bin5     rm -f uart_elf spi.o6 7 clean:8     rm -f spi.bin

Run make to write the generated SPI. binfile to NAND flash through BIOS,Transient the MoSi and miso pins, Starts from NAND Flash.