Arm bare metal Development (iii) SDRAM Programming

The following bare metal program is based on gt2440 and the compiler is a arm-linux-gcc-4.4.3.

Program Structure: The program consists of SDRAM. S and Main. C consists of two files, SDRAM. s file to complete some initialization work, such as clock initialization, memory controller initialization, copy the second-stage code to SDRAM, and so on; Main. C is responsible for four LEDs which are cyclically lit and extinguished.

Program process: during power-on, the CPU automatically jumps to the reset exception vector entry. In the reset exception handling process, the CPU first closes the watchdog, then initializes the system clock, initializes the memory controller, and copies the second-stage code to the SDRAM, finally, jump to the SDRAM and execute the main () function.

 

SDRAM. S:

1 # define mem_reg_start 0x48000000 2 # define sdram_base 0x30000000 3 4 # define locktime limit 5 # define mpllcon limit 6 # define upllcon limit 7 # define clkdivn 0x4c000014 8 # define camdivn 9 10 # define wtcon 0x53000000 11 12 13. section. text 14. global _ start 15 _ start: 16 B reset 17 18 @ reset Exception Handling 19 Reset: 20 @ disable watchdog 21 BL disable_watchdog 22 @ initialize clock 23 BL init_clock 24 @ initialize memory controller 25 BL init_sdram 26 @ copy Stage 2 code to SDRAM 27 BL copy_to_sdram 28 29 ldr pc, = on_sdram 30 on_sdram: 31 @ set the treasure pointer 32 LDR sp, = 0x34000000 33 @ jump to the main () function 34 BL main 35 loop: 36 B loop @ infinite loop 37 38 39 disable_watchdog: 40 LDR r0, = wtcon 41 Bic R1, R0, #0x20 42 STR R1, [R0] 43 44 mov PC, LR 45 46 init_clock: 47 LDR r0, = locktime 48 LDR R1, = 0x00ffffff 49 STR R1, [R0] 50 @ clock division 51 LDR r0, = clkdivn 52 LDR R1, = 0x05 53 STR R1, [R0] 54 @ asynchronous bus mode 55 MRC P15, 0, R1, C1, C0, 0 56 Orr R1, R1, #0xc0000000 57 MCR P15, 0, R1, C1, C0, 0 58 @ fclk = 400 MHz, hclk = 100 MHz, pclk = 50 MHz 59 LDR r0, = mpllcon 60 LDR R1, = 0x5c011 61 STR R1, [R0] 62 @ upll = 48 MHz 63 LDR r0, = upllcon 64 LDR R1, = 0x38022 65 STR R1, [R0] 66 67 mov PC, LR 68 69 copy_to_sdram: 70 LDR r0, = 2048 @ start address (source address) of the code to be copied 71 LDR R1, = sdram_base @ address to be copied (Destination Address) 72 add R3, R0, #2*1024 @ copy size (2 k) 73 copy_loop: 74 LDR R2, [R0], #4 75 STR R2, [R1], #4 76 CMP r0, R3 77 BNE copy_loop 78 79 mov PC, LR 80 81 init_sdram: 82 LDR r0, = mem_reg_start 83 adrl R1, mem_1__val 84 add R2, R0, #52 // 13 registers, each of which occupies 4 bytes (13*4) 85 mem_1__loop: 86 LDR R3, [R1], #4 87 STR R3, [R0], #4 88 CMP r0, R2 89 BNE mem_1__loop 90 91 mov PC, LR 92 93 @ register configuration value 94. align 4 95 mem_1__val: 96. long 0x22011110 // bwscon 97. long 0x00000700 // bankcon0 98. long 0x00000700 // bankcon1 99. long 0x00000700 // bankcon2100. long 0x00000700 // bankcon3101. long 0x00000700 // bankcon4102. long 0x00000700 // bankcon5103. long 0x00018005 // bankcon6104. long 0x00018005 // bankcon7105. long 0x008c04f4 // refresh (hclk = 100 MHz) 106. long 0x000000b1 // banksize107. long 0x00000030 // mrsrb6108. long 0x00000030 // mrsrb7

Main. C:

1 # define gpbcon (* (volatile unsigned long *) 0x56000010) 2 # define gpbdat (* (volatile unsigned long *) 0x56000014) 3 # define gpbup (* (volatile unsigned long *) 0x56000018) 4 5 # define ngpb_output (1 <10) | (1 <12) | (1 <14) | (1 <16) 6 7 // latency function 8 void delay () 9 {10 int I = 0 xFFFF; 11 Int J; 12 For (j = 0; j <I; j ++); 13 14} 15 16 // main function 17 int main (void) 18 {19 // IO port configured to output 20 gpbcon = ngpb_output; 21 22 while (1) 23 {24 gpbdat = 0x0; // output low level (light up led) 25 delay (); // latency 26 gpbdat = 0 xffffffff; // output high level (off led) 27 delay (); // latency 28} 29 30 return 0; 31}

Makefile:

 1 objs := sdram.S main.c 2  3 sdram.bin:$(objs) 4     arm-linux-gcc -c -o sdram.o sdram.S 5     arm-linux-gcc -c -o main.o main.c 6     arm-linux-ld -Tsdram.lds -o sdram_elf  7     arm-linux-objcopy -O binary -S sdram_elf sdram.bin 8  9 clean:10     rm -f sdram_elf sdram.bin *.o

Link script SDRAM. LDS:

1 SECTIONS2 {3     nand  0x00000000 : {sdram.o}4     sdram 0x30000000 : AT(2048) {main.o}5 }

Run make to download the SDRAM. binfile to NAND flash through bios and start it from NAND Flash.