Arm compilation – (2) ARM program status Register

By:ailson Jack.

date:2016.04.14

Personal blog: www.only2fire.com

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ARM's program status register CPSR reflects the status of the current processor, which contains:

1), 4 condition Code flags (negative (N), 0 (Z), Carry (C), and Overflow (V));

2), 2 interrupt stop bit, control one type of interrupt respectively;

3), a bit used to indicate the current execution instruction (arm or thumb);

4), 5 bits encoded on the current processor mode.

The register format of the CPSR is shown below:

1. Condition Code Flag

In the arm state, the majority of instructions are conditional execution, in the thumb state, only the branch instruction (B, BL, BX) is conditional execution.

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