Arm CPSR + spsr

1. Introduction

CPSR (current Program Status Register) is accessed in any processor mode. It includes [condition flag], [interrupt prohibition bit], [current processor mode flag], and some other control and status bits. Each processor mode has a dedicated physical status register called spsr (backup program status register ).

When a specific exception interrupt occurs, this register is used to store the content of the current program status register. You can use spsr to restore CPSR when an exception is terminated. Because the user mode and system mode are not the exception interrupt mode, there is no spsr. When users access spsr in user mode or system mode, unpredictable consequences will occur.

2. CPSR format

The CPSR format is as follows. The format of spsr is the same as that of CPSR. Shows the CPSR format:

3. Condition code mark

N, Z, C, and V are condition code signs. Their contents can be changed by the results of arithmetic or logical operations, and can determine whether a command is executed. The meanings of the condition codes are shown in the following table:

Flag Space	Description
N	When two signed integer operations are performed: N = 1: indicates that the calculation result is a negative number; n = 0: indicates that the calculation result is a positive number or zero.
Z	Z = 1 indicates that the calculation result is zero, and z = 0 indicates that the calculation result is non-zero. For CMP commands, the two numbers in the z = 1 table are equal.
C	You can set the value of C in four ways: In addition commands (including comparison command CMP), when the result produces carry, c = 1 indicates that the unsigned operation overflows. In other cases, c = 0. In the subtraction command (including the subtraction command CMP), when the bitwise occurs in the operation, c = 0 indicates that the number of unsigned operations overflows; in other cases, c = 1. For non-alkali operation commands containing shift operations, C contains the value of the last overflow bit. For other non-addition or subtraction operation commands, the C-bit value is usually not affected.
V	For addition and subtraction operation commands, when the operands and operation results are binary complement numbers, V = 1 indicates that the symbols are overflow. Generally, other commands do not affect the V bit.

4. Control bit

CPSR's low octal I, F, T, and m [] are collectively referred to as control spaces. These bits change when an exception is interrupted. In privileged processor mode, software can modify these control bits.
1) I: IRQ interruption prohibited bit: When I = 1, IRQ interruption is prohibited,

2) F: FIQ interruption prohibited bit: When F = 1, FIQ interruption prohibited
3) T: The t control bit reflects the running status of the processor. When this bit is 1, the program runs in the thumb state; otherwise, the program runs in the arm state. The signal is reflected on the external pin Tbit. The Tbit bit in CPSR cannot be modified in the program; otherwise, the processor's working status cannot be determined.
4) reserved bits: The remaining bits in CPSR are reserved bits. When the condition code flag or control bits in CPSR are changed, do not change the reserved bits, and do not store data with the reserved bits in the program. Reserved bits are used for expansion of the arm version.
5) run mode bit M []: The bit is the mode bit, which determines the run mode of the processor. The meanings are shown in the following table:

M [4: 0]	Processor Mode	Accessible registers in arm Mode	Accessible registers in thumb Mode
0b10000	User Mode	PC, CPSR, R0 ~ R14	PC, CPSR, R0 ~ R7, LR, SP
0b10001	FIQ Mode	PC, CPSR, spsr_fiq, r14_fiq ~ R8_fiq, R0 ~ R7	PC, CPSR, spsr_fiq, lr_fiq, sp_fiq, R0 ~ R7
0b10010	IRQ Mode	PC, CPSR, spsr_irq, r14_irq ~ R13_irq, R0 ~ R12	PC, CPSR, spsr_irq, lr_irq, sp_irq, R0 ~ R7
0b10011	Management Mode	PC, CPSR, spsr_svc, r14_svc ~ R13_svc, R0 ~ R12	PC, CPSR, spsr_svc, lr_svc, sp_svc, R0 ~ R7
0b10111	Stop Mode	PC, CPSR, spsr_abt, r14_abt ~ R13_abt, R0 ~ R12	PC, CPSR, spsr_abt, lr_abt, sp_abt, R0 ~ R7
0b11011	Undefined Mode	PC, CPSR, spsr_und, r14_und ~ R13_und, R0 ~ R12	PC, CPSR, spsr_und, lr_und, sp_und, R0 ~ R
0b11111	System Mode	PC, CPSR, R0 ~ R14	PC, CPSR, LR, SP, R0 ~ R74