Arm exceptions and interruptions

Source http://blog.csdn.net/wojiwoye/archive/2010/04/16/5491624.aspx

I would like to thank wojiwoye, but it seems that he has also reprinted it. The original author of this article cannot find it... sorry ~

Type of abnormal interruption in arm:

Abnormal interrupt name	Description
Reset (reset)	When the reset pin of the processor is valid, a reset exception interrupt occurs, and the program jumps to the reset exception interrupt handler for execution. Reset exception interruptions are usually used in the following situations: 1. When the system is powered on 2. system reset 3. Jump to the reset interrupt vector for execution, called soft Reset
Undefined command	When the ARM processor or the coprocessor in the system determines that the current instruction is undefined, an exception interruption occurs. You can use this abnormal interrupt mechanism to simulate floating point vector operations.
Software interruption (Software interrupt SWI)	This is a user-defined interrupt command. It can be used by a program in user mode to call privileged operation commands. This mechanism can be used in Real-time Operating Systems (RTOs) to call system functions.
Command prefetch aborted (Prefech abort)	If the prefetch instruction address of the processor does not exist, or the address does not allow access to the current instruction, when the prefetch instruction is executed, the processor generates an exception in command prefetch interruption.
Data Access aborted (Data abort)	If the target address of the data access command does not exist, or the address does not allow access to the current command, the processor will abort the data access and interrupt the operation.
External Interrupt request (IRQ)	When the processor's external interrupt request pin is valid and the I control bit of the CPSR register is cleared, the processor generates an external interrupt request (IRQ) exception interrupt. In the system, each peripheral usually requests the processor service through this exception.
Fast request interruption (FIQ)	When the processor's external fast interrupt request pin is valid and the F control bit of the CPSR register is cleared, the processor generates an external interrupt request (FIQ) with an exception

Response Process of the ARM processor to abnormal interruptions:

1. The Response Process of the ARM processor to abnormal interruptions is described as follows.
2. Saves the current status of the processor, the interrupt shielding bit, and the flag of each condition. This is achieved by saving the contents of the CPSR of the current program status register to the spsr register corresponding to the exception interrupt to be executed. Each exceptional interrupt has its own physical spsr register.
3. Set the corresponding bit in the CPSR of the current program status register. Including: Set the bit in CPSR to enable the processor to enter the corresponding execution mode; set the bit in CPSR to disable IRQ interruption. When it enters the FIQ mode, disable FIQ interruption.
4. Set the register ir_mode to the return address.
5. Set the program counter value (PC) to the interrupt vector address of the exception interrupt to jump to the corresponding exception Interrupt Processing Program for execution.

The above processor can use the following pseudocode to describe the response process to abnormal interruptions.

R14 _ <prediction_mode> = return link

Spsr _ <prediction_mode> = CPSR

CPSR [4: 0] = expection mode number

/* Disable new FIQ interruptions when a FIQ exception is interrupted */

If <prediction_mode >== reset or FIQ then

CPSR [6] = 1

/* Disable IRQ interruption */

CPSR [7] = 1

/* Jump the program counter to the code segment pointed to by the vector table */

PC = Exception vector address

Return from the exception interrupt handler:

1. Restores the processor status of the program to replicate the content of the spsr_mode register to CPSR.
2. Return to the next instruction of the command with an exception interruption, and copy the ir_mode register to the program counter PC.

Note: The reset exception interrupt handler does not need to be returned. The entire user program is executed when the exception interrupt handler is reset, so it does not need to be returned (I don't understand what I 've mentioned here. refer to the information I 've found below)

-- All the above content is taken from du chunlei's Ar architecture and Programming

Note: The reset exception interrupt processor program does not have the corresponding spsr. Therefore, you only need to set the status bit to user mode when returning, and then jump to the next code at the interrupt location.

Appendix:Arm exceptions and interruptions

The ARM processor has seven major exceptions (two interrupt exceptions ):

1. Reset exception. In an arm-core microcontroller, the following events are often used as the cause of the reset.

• Power-on Reset: After power-on, reset to bring the internal status to a predetermined state, especially when the program jumps to the initial entry;

• Reset pulse on the reset pin: This is caused by other external control signals;

• Detects over-voltage or undervoltage for system power supply;

• Abnormal clock reset.

After the ARM processor is reset, the processor hardware performs the following operations:

• Enter the management mode forcibly;

• Forcibly enters the arm status;

• Jump to the absolute address Pc = 0x00000000 for execution;

• IRQ interruption and FIQ interruption are prohibited.

After resetting, the Program Status Register is as follows:

......	I	F	T	M4	M3	M2	M1	M0
	1	1	0	1	0	0	1	1

After the power-on reset, enter the management mode and execute the operating system program. It is usually used for system initialization, such as opening or stopping. then switch to the user mode and start executing the normal user program.

You can use the following programs to switch to user mode:

Mrs r0, CPSR; read Status Register
Bic r0, R0, #03; clear the last two digits 0
MSR cprs_c, R0; load the modified value to the Status Register. The switching is over.
...... User program

2. Unknown command exception. Because arm uses 32-bit code, it contains a large amount of information, up to 31 (4 GB) of 2 ). Arm instruction sets cannot use up all code. When the ARM processor encounters a command that cannot be decoded, it will issue

An error occurred while generating undefined commands. Enter the interrupt processing program.

Arm's undefined command has the following two exceptions:

(1) An unexecutable command is not defined;

(2) execute an operation command on the coprocessor. Under normal circumstances, the coprocessor should respond, but the coprocessor does not.

When an exception interrupt is not defined, the F-bit in the Status Register remains unchanged. Run the following command to exit the abnormal interrupt and return to the original program.

• Copy the address of the next instruction to LR;

• Copy the Program Status Register CPSR to spsr_und;

• Force enter the undefined mode;

• Forced Entry to arm mode;

• Jump to the absolute address Pc = 0x00000004 for execution;

• Disable IRQ interruption.

After an interruption occurs, the Program Status Register is as follows:

......	I	F	T	M4	M3	M2	M1	M0
	1	X	0	1	1	0	1	1

Movs PC, R14.

3. software interruption exceptions are caused by command SWI. After the program executes this command, an exception is interrupted. When the processor responds to an interruption, the hardware performs the following operations.

• Copy the address of the next instruction to LR;

• Copy the Program Status Register CPSR to spsr_svc;

• Enter the management mode forcibly;

• Forcibly enters the arm status;

• Jump to the absolute address Pc = 0x00000008 for execution;

• Disable IRQ interruption.

The Program Status Register after the program is interrupted is as follows:

......	I	F	T	M4	M3	M2	M1	M0
	1	X	0	1	0	0	1	1

After the software interrupt processing program is completed, use the following command to return to the original center: movs PC, R14.

4. prefetch refers to a stop exception. A stop exception caused by program memory is called a prefetch exception. A stop exception caused by data storage is called a data stop exception. Since the arm command is a three-level pipeline structure, read

The instruction fetch cycle is performed in advance. Therefore, the instruction reading process is generally called prefetch. If the program memory sends a stop signal while obtaining the command, the ARM processor will invalidate this command flag and wait for the execution

Line. There are two possible reasons:

• When the program jumps before executing this command, this invalid command will not cause abnormal interruption;

• When this command is executed, the processor will initiate a prefetch, indicating that an exception is aborted, causing interruption.

When a prefetch occurs, the processor hardware responds to an interruption and performs the following operations:

• Copy the IP address of the PC to LR during the interruption;

• Copy the Program Status Register CPSR to spsr_abt;

• Forcibly enters the abort exception mode;

• Forcibly enters the arm status;

• Jump to the absolute address Pc = 0x0000000c for execution;

• Disable IRQ interruption.

After an interruption occurs, the Program Status Register is as follows:

......	I	F	T	M4	M3	M2	M1	M0
	1	X	0	1	0	1	1	1

Prefetch refers to the execution of the following commands when an exception is aborted and an interruption is returned: subs PC, R14, #4.

5. Data abort exception. When the ARM processor accesses the data storage, the data storage sends a abort signal while reading the data, causing a data abort exception.

Use the following command when the service program returns a data abort exception:

Subs PC, R14, #8

The preceding command is returned to the Command executed at the time of interruption. The purpose is to read data from the data storage again. If you no longer read data, execute the next command and use the following command to return it:

Subs PC, R14, #4

• Copy the IP address of the interrupted PC to LR;

• Copy the Program Status Register CPSR to spsr_abt;

• Forcibly enters the abort exception mode;

• Forcibly enters the arm status;

• Jump to the absolute address Pc = 0x00000010 for execution;

• Disable IRQ interruption.

After an interruption occurs, the Program Status Register is as follows:

......	I	F	T	M4	M3	M2	M1	M0
	1	X	0	1	0	1	1	1

6. interrupt request (IRQ) exceptions, such as timer interruption, serial port communication interruption, external signal interruption, and A/D processing interruption. IRQ interruption is shielded. The I-bit in the Status Register is the shielding bit of IRQ.

. When I = 1. The IRQ interrupt is blocked. If I = 0, the interrupt is allowed. When the processor resets the rear I to 1, the interrupt is disabled.

When IRQ is interrupted, the processor's Hardware response is interrupted and the following operations are performed:

• Copy the IP address value of the PC during interruption to LR;

• Copy the Program Status Register CPSR to spsr_irq;

• Force enter the IRQ exception mode;

• Forcibly enters the arm status;

• Jump to the absolute address Pc = 0x00000018 for execution;

• Disable IRQ interruption.

After an interruption occurs, the Program Status Register is as follows:

......	I	F	T	M4	M3	M2	M1	M0
	1	X	0	1	0	0	1	0

After the interrupt processing is completed, the program executes the following to return the original center: subs PC. R14, #4.

7. The fast interrupt (FIQ) request is abnormal; The FIQ fast interrupt is shielded. The F bit in the Status Register is the shielding bit of FIQ. When F = 1. The FIQ interrupt is blocked. If f = 0, the interrupt is allowed. Processor Replay

If the value of F is 1, the interrupt is disabled.

When IRQ is interrupted, the processor's Hardware response is interrupted and the following operations are performed:

• Copy the IP address value of the PC during interruption to LR;

• Copy the Program Status Register CPSR to spsr_fiq;

• Force enter the FIQ exception mode;

• Forcibly enters the arm status;

• Jump to the absolute address Pc = 0x0000001c for execution;

• Disable FIQ interruption.

After an interruption occurs, the Program Status Register is as follows:

......	I	F	T	M4	M3	M2	M1	M0
	1	X	0	1	0	0	0	1

After the interrupt processing is completed, the program executes the following to return the original center: subs PC. R14, #4