Arm Instruction Set-starting with Assembly

Features:
Load/Store Structure (memory operations only include load and store, and all other operations are completed in registers)
32-Bit fixed instruction width
3. Address Instruction format (both source operands and result registers are specified independently)
Each Command is executed in a condition.
A normal operation and a normal ALU operation can be completed simultaneously in a single instruction executed in a single cycle.

Automatic address change

Register Model
In User Mode
15 32-bit universal register heap for R1-R15, R15 for PC register
CPSR Status Register four-digit (N), Z (0), C (carry), V (overflow) Flag

Classification:
+ ------------- + ----------- +
| Data Processing Instruction | data transmission instruction | control flow instruction |
+ ------------- + ----------- +

------------------------------------------------------------------------------
Data processing commands: perform arithmetic or logical operations on data in registers
Simple register operation
Arithmetic Operation: add, ADC, sub, SBC, RSB, RSC
Note: RSB and RSC are inverse subtraction and Inner Inverse subtraction, respectively.
Example: Add r0, R1, R2; R0 = R1 + R2
RSB r0, R1, R2; R0 = R2-r1
Logical operations by bit: And, Orr, EOR, Bic
Note: bitwise AND, bitwise OR, bitwise OR, and not
Example: Bic r0, R1, R2; R0 = R1 and not r2
Register transfer operation: mov, MVN
Note: MVN is a bitwise reverse transfer.
Example: MVN r0, R2; R0 = Not r2
Comparison: CMP, CEN, TST, TEQ
Note: comparison, reverse comparison, bit test, and test are equal
Example: TEQ R1, R2;
Note: The sequential format of operands is the result register, the first and second operands.
Immediate count operation:
Note: Add # to the front of the number to indicate the immediate number, and add # & to indicate the hexadecimal instant number.
Example: Add R3, R3, #1; R3 = R3 + 1
And R8, R7, # & ff; R8 = R7 & 0xff
Register shift operation: Four address commands
Shift command: LSL, LSR, ASL, ASR, Ror, rrx
Description: Logical shift left, logical shift right, arithmetic shift left, arithmetic shift right, cyclic shift right, and extension
One-digit cycle shifts right
Example: Add R3, R2, R1, LSL #3; R3 = r2 + (R1 <3)
Set the condition code:
Note: you can set a condition code (nzcv) for any data processing commands. You can only set a condition code for comparison operations.
Set the condition code. If you want to set the condition code for other data processing operations, you need to add s
Operation code.
Arithmetic Operations (including CMP and CEN) are used to set all flags Based on arithmetic operation results.
Bit, logical and transfer operations do not produce meaningful C or v values.
If n and Z are set, V is retained. If no shift operation is performed, C is retained.
To C.
Example: adds R2, R2, R0
ADC R3, R3, r1
Multiplication operation:
Note: The second operand cannot be an immediate number.
The result register cannot be the source register.
If the bit s is set, the flag V is retained, and the flag C is no longer meaningful.
For long multiplication, the 32-bit high valid bit is placed in the second result register.
Example: Mul R4, R3, R3; r4 = R3 * r2
MLA R4, R3, R2, R1; r4 = R3 * r2 + r1

------------------------------------------------------------------------------
Data transfer command: transfers data between ARM registers and memory
Basic Data Transmission commands
Load/Store commands for a single register
Multi-register load/store commands
Single Register switch command: It is mainly used in system-level programs to implement atomic operations.
Addressing Mode: arm's data transmission Commands include indirect addressing of registers, base offset, and base address change,
Note: In any situation, an arm register is required to store the address, which is close
The address of the data to be transferred.
Example: LDR r0, [R1]; the content of the memory location represented by the value in R1 is read into R0
STR r0, [R1]; write R0 to the memory location represented by a numerical value in r1

Pre-indexed)
Note: The base address register does not contain a definite address. The base address cannot exceed 4 kb.
Offset to address
Example: LDR r0, [R1, #4]; Addressing R1 + 4
The front address of the automatic address change:
Note: When the address is changed automatically, the base address register is modified at the same time.
Example: LDR r0, [R1, #4]! Address R1 + 4 and set R1 + = 4
Post-address change (post-indexed)
Note: No offset addressing is added to the base address. The offset is used only as the base address correction.
Example: LDR r0, [R1], #4; Addressing R1, and adding R1 + = 4
Arbitrary byte alignment command: ldrb

Multi-register data transfer and block transfer (block transfer omitted)
Note: several registers are simultaneously accessed, and a single entry is allowed for any sub-sets of 16 registers.
Command Transmission. Supports automatic address change
Example: ldmia R1, {r0, R2, R5}; Replace [R1], [R1 + 4], [R1 + 8]
Read r0, R2, R5

------------------------------------------------------------------------------
Control Flow commands
Transfer Instruction (Branch)
Note: unconditional transfer of B and bal
Example: B label; label is a location
Conditional transfer
Note: beq is equal.
BNE
BPL non-negative
Negative BMI
BCC without carry
BCS has a forward position
BlO smaller than (unsigned number)
BHS greater than or equal to (unsigned number)
BHI greater than (unsigned number)
Limit is less than or equal to (unsigned number)
BVC No overflow (number of symbols)
BVS overflow (signed number)
Bgt is greater than (number of symbols)
BGE greater than or equal to (number of symbols)
BLT less than (number of symbols)
Ble less than or equal to (number of symbols)
It is the same as the binary code of BCC, blo, BCS, and BHS.
Conditional execution
Note: sometimes conditional execution can be used instead of transfer. Conditional execution must be 3 characters long.
The operation code is followed by a 2-character condition code. The condition code should be in any other
Before the correction code.
Example: CMP r0, #5
Addne R1, R1, R0
Subne R1, R1, R2
; In R0! = 5, the subsequent addition and subtraction statements will be executed
Transfer and link instructions and subprogram return instructions
Note: It is used to jump and return, such as subprograms and Bl commands. Note that subprograms cannot be nested,
Otherwise, the return address at the upper level will be overwritten by the return address at the lower level.
Save the returned address and variable to the stack and use javasfd and ldmfd.
Monitoring Program call (omitted)
Description: Soft Interrupt related, which can be used to provide Io access
Jump table (omitted)
Note: When the subprogram list is longer, check that the jump table is out of bounds.

------------------------------------------------------------------------------
References
The second version of arm SOC architecture, Steve furber