Arm register Introduction

How many registers does the ARM processor contain? What registers are available in each mode? What are the functions of these registers? Let's learn about arm registers with these questions! I believe you will gain some benefits after reading this article.
The ARM processor has 37 registers.
It contains 31 General registers and 6 State registers.

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USR System Supervisor abort undefined IRQ FIQ
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R0 R0 R0 R0 R0 R0 R0
R1 R1 R1 R1 R1 R1 R1 r1
R2 R2 R2 R2 R2 r2
R3 R3 R3 R3 R3 R3 r3
R4 R4 R4 R4 R4 r4
R5 R5 R5 R5 R5 R5 R5 R5
R6 R6 R6 R6 R6 R6 R6
R7 R7 R7 R7 R7 R7 r7
R8 R8 R8 R8 R8 R8 r8_fiq
R9 R9 R9 R9 R9 R9 r9_fiq
R10 R10 R10 R10 R10 R10 r10_fiq
R11 R11 R11 R11 R11 R11 r11_fiq
R12 R12 R12 R12 R12 R12 r12_fiq
R13 R13 r13_svc r13_abt r13_und r13_irq r13_fiq
R14 R14 r14_svc r14_abt r14_und r14_irq r14_fiq
PC
CPSR
Spsr_svc spsr_abt spsr_und spsr_irq spsr_fiq
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1. General Register Classification:
A. Registers not backed up, including R0-R7
For each unbacked register, all modes refer to the same physical register (for example, R0 in USR and R0 in FIQ are the same register ). During mode switching due to abnormal program interruption, the same physical register is used in different modes. This may cause data to be damaged. Non-Backup registers are not used by the system for other purposes and can be used in any case without backup registers.
B. Backup registers, including R8-R14
For the backup register R8-R12, all modes except FIQ use the same physical register. In FIQ mode, r8_fiq, r9_fiq,
R10_fiq, r11_fiq, r12_fiq. It has its own physical register.
For R13 and R14 registers, each mode has its own physical registers (the system and usr registers are the same). When an exception occurs, the system uses the physical registers in the corresponding mode, this prevents data corruption.
R13 is also called the SP Stack pointer.
R14 is also called the LR register.
C. Program counters, PC
The instruction address of the PC register is stored. Because arm uses the streamline mechanism to execute the instruction, the PC register always stores the address of the next instruction.
Because arm is aligned by words, bit [1:0] After PC reading is always 0b00 (the bit [0] of thumb is 0b0 ).

2. Program Status Register
The Program Status Register includes the current program Status Register and the backup Status Register.
A. CPSR (Program Status Register)
CPSR can be accessed in any processor mode. Its structure is as follows:

31 30 29 28 --- 7 6-4 3 2 1 0
N z c v I f M4 m3 m2 M1 M0

N (negative), Z (zero), C (carry), and V (overflow) are called condition flags. The arm command is executed selectively based on the condition flag of CPSR.

CPSR condition flag
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Condition flag meaning
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N = 1 indicates that the calculation result is a negative number, and n = 0 indicates that the calculation result is a positive number.
Z = 1 indicates that the calculation result is 0, and z = 0 indicates that the calculation result is non-zero.
C = 1 indicates that the computation result produces carry.
The symbol bit of the result of the V v = 1 operation overflows.
Q in the armv5 eseries, q = 1 indicates that the DSP command overflows.
In earlier versions of armv5, there is no Q flag.
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The following command affects the condition flag of CPSR
(1) Comparison commands, such as CMP, CEN, TEQ, and TST.
(2) When the destination register of some arithmetic logic operations is not a PC, these commands will affect the condition flag of CPSR.
(3) The MSR and Mrs commands can operate on CPSR and spsr.
(4) the LDM command can copy the spsr to the CPSR.

CPSR control bit
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Control bit meaning
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I I = 1 disable Iro interrupt
F = 1 disable FIQ interrupt
T armv4 and later versions T = 0 execute the arm command, T = 1 execute the thumb command.
For non-T versions above armv5, T = 0 executes the arm command. T = 1 indicates that the next command produces undefined command interruption. M [4: 0] Control Processor Mode
0b10000 user
0b10001 FIQ
0b10010 IRQ
0b10011 Supervisor
0b10111 abort
0b11011 undefined
0b11111 System
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B. spsr (Backup Status Register)
The structure of spsr is the same as that of CPSR. spsr is used to back up CPSR.
Now you have some knowledge about ARM processor registers?