ARM--I2C

The s5pc100's Proteus microprocessor supports multi-host I2C bus serial interfaces. A dedicated serial data cable (SDA) and a serial clock line (SCL) transmit information between the bus host and peripheral devices connected to the I2C bus. The SDA and SCL lines are bidirectional.

In multi-host I2C bus mode, multiple microprocessors are sent to or received from the slave device. The host s5pc100 starts and terminates a data transmission on the I2C bus. The I2C bus on s5pc100 uses a standard bus arbitration program.

To control multi-host I2C bus operations, the value must be written to the register:

Multi-host I2C control register i2ccon

Multi-host I2C control/Status Register i2cstat

Multi-host I2C send/receive conversion register i2cds

Multi-host I2C address register i2cadd

If the I2C bus is idle, the SDA and SCL lines should be both high. When the SCL line is stable at high-frequency, the SDA line level starts from high to low conversion, and the SDA line level starts to stop.

Host devices always generate Start and Stop conditions. When the start condition is initiated, the 7-bit address value of the First Data byte on the bus determines the slave device selected by the bus host device. The second digit determines the transmission direction (read/write ).

Each Data byte put on the SDA line should be a total of eight bytes. There is no limit on the number of data bytes sent or received during bus transmission. Data is always sent from the highest valid bit MSB, and each word is followed by the response bit ack.

 

S5pc100 I2C bus interface has four operation modes:

Host sending mode; host receiving mode; slave sending mode; slave receiving mode

Functions of these operation modes:

Start and Stop Conditions

If the I2C bus interface is not started, it is usually in the slave mode. In other words, the interface should be in the off-machine mode before detecting the SDA online start condition (when the clock signal of the SCL line is high, the SDA line level starts from high to low conversion. If the interface status is switched to the host mode, the online data transmission of SDA can be initiated and the SCL signal is generated.

One-byte serial data is transmitted through the SDA line, and the condition is stopped to terminate data transmission. When the clock signal of the SCL line is high, the SDA line level starts the stop condition from low to high. Host generation start and stop conditions. If conditions are generated at the beginning, the I2C bus changes to the busy state. Stop conditional release I2C bus. If the host initiates a start condition, a slave address should be sent to notify the slave device, A byte address field contains a 7-bit address value and a 1-bit Transmission Direction Indication value (write or read ). If the 8th-bit value is 0, it indicates a write operation (sending operation). If the 8th-bit value is 1, it indicates a read data request (receiving operation ).

The host sends a stop condition to complete the transmission operation. If the receiver box continues sending bus data, another start condition and slave address should be generated. In this way, you can perform read and write operations in various formats.

 

 

Data Transmission Format

Each byte on the SDA line should be 8 bits in length, and there is no limit on the number of bytes sent each time. The first byte following the start condition should contain the address field. If the I2C bus operation is in host mode, the host sends the address domain. Each word segment should be followed by an ACK. MSB, the highest valid bits of the serial data and address, should be sent first.

Send Response Signal

To complete one-byte transmission, the receiver sends an ACK to the sender. The response pulse is generated in the 9th clock cycle of the SCL line. One-byte data transmission uses eight clocks. The host sends an ACK to generate a clock pulse.

 

If the sender receives an ACK, the SDA line is released by setting the SDA Line High. The receiver pushes the SDA line down during the ACK clock pulse of the response bit to keep the SDA line low between the 9th pulse cycle of the SCL line.

The software (i2cstat) enables or disables the ACK sending function. However, the ACK pulse at the 9th pulse cycle of the SCL line is requested to complete one-byte data transmission.

 

Read/write operations

In sending mode, if data is transmitted, the I2C bus interface waits until the I2C bus data conversion register (i2cds) receives a new data. Before the new data is written to the register, the SCL line remains low and is released after being written. S5pc100 gets interrupted to identify whether the current data is sent completely. After receiving the interrupt request, the CPU writes a new data to the i2cds register.

In the receiving mode, if the data is received, the I2C bus interface waits until the I2C bus data conversion register (i2cds) is read. Before the new data is read, the SCL line remains low and then read and released. S5pc100 gets an interruption to identify whether the current data reception is complete. The CPU reads data from the i2cds register after receiving the interrupt request.

Bus Arbitration Program

Arbitration occurs on the SDA line to prevent conflicts between two hosts on the bus. If an SDA Line High-Level host detects another SDA line low-level host, it will not initiate data transmission, because the current level on the bus cannot correspond to itself, the arbitration program delays until the SDA line level increases.

If the host simultaneously lowers the SDA line level, no host evaluates whether the master control is on its own. To evaluate the detection address bit of each host. When each host generates a slave address, the address bit on the SDA line is detected because the SDA line is likely to gain a low level rather than maintaining a high level. Assume that one host generates a low level as the address first, and the other host remains at a high level. In this case, the two hosts detect a low level on the bus because the low level is better than the high level. If this happens, the host that generates a low level (as the first address) obtains the master control permission, and the host that generates a high level (as the first address) withdraws the master control permission. If the host generates a low level as the first address, then the second address is arbitrated. This kind of Arbitration continues until the end of the address bit.

 

Conditions for Suspension

If the recipient of the slave fails to respond to the confirmation from the slave address, the SDA line remains high. In this case, the host generates a stop condition and then terminates the transmission.

If the host receiver is busy with paused transmission, it will cancel generating a response ack after receiving the final data bytes from the slave to send a signal. Release the SDA line from the sender to allow the host to generate a stop condition.

 

Configure I2C bus

　　

To control the clock frequency of the serial bus, the four-bit pre-division value is written into the i2ccon register. The I2C bus interface address is stored in the I2C BUS address (i2cadd) Register (by default, the I2C bus interface address has an unknown value ).

Operation flowchart in each mode

The following steps are executed in each I2C send/receive operation.

1. If needed, go to your slave address to the i2cadd register.

2. Set the i2ccon register

A enable interruption

B. Define the SCL period.

3. Set i2cstat to enable Serial Output

# Include "s5pc100. H"

Void putc (const char data)
{
While (! (Uart0.utrstat0 & 0x2 ));
Uart0.utxh0 = data;
If (Data = '\ n ')
Putc ('\ R ');
}
Void puts (const char * pstr)
{
While (* pstr! = '\ 0 ')
Putc (* pstr ++ );
}

Void uart0_init (void)
{
Gpa0.gpa0con = (gpa0.gpa0con &~ (0xff) | 0x22; // enable gpa0.0 gpa0.1 pin function mode // rxd0 txd0
Uart0.ufcon0 = 0x00; // disable FIFO
Uart0.umcon0 = 0x00; // disable AFC
Uart0.ulcon0 = 0x03; // Data Length 8 bit
Uart0.ucon0 = 0x305 ;//
Uart0.ubrdiv0 = 0x23; // baud rate divisior register 115200 ubrdiv0 = (pclk/(BPS x 16 ))
Uart0.udivslot0 = 0xddd5; // set slot register generate more accurate baud rate
Printf ("Open UART device OK! \ N ");
}

 

# Include "s5pc100. H"
# Include "UART. H"

/****
* Functioal: Reading the value of the internal lm75 register
* Param: Address Register of the internal lm75 register
* Return: value of the internal lm75 register
*/
Int set_pointer_and_read_temperature (void)
{

Int delay;
Int low, high;
I2c0. i2cds0 = 0x90;/* lm75 slave address */
I2c0. i2ccon0 = 0xe0;/* enable ack bits, prescaler: 512, Rx/TX interrupt enable ,*/
I2c0. i2cstat0 = 0xf0;/* master trans mode, start, enable Rx/Tx ,*/
While (! (I2c0. i2ccon0 & (1 <4);/* The End Of The waiting to be sent */
 
I2c0. i2cds0 = 0x0;/* pointer register temperature (read only) send address of sfr in the lm75 */
I2c0. i2ccon0 & = ~ (1 <4);/* clear pending condition & resume the operation */
While (! (I2c0. i2ccon0 & (1 <4);/* The End Of The waiting to be sent */
 
I2c0. i2cds0 = 0x90;/* again to send lm75 salve address */
I2c0. i2cstat0 = 0xb0;/* master receive mode, start, enable Rx/Tx ,*/
I2c0. i2ccon0 & = ~ (1 <4);/* clear pending condition & resume the operation */
While (! (I2c0. i2ccon0 & (1 <4);/* The End Of The waiting to be sent */

I2c0. i2ccon0 & = ~ (1 <4);/* clear pending condition & resume the operation */
For (delay = 0; delay <0 xFFFF; delay ++ );
High = i2c0. i2cds0;/* read temperature of high 8 bit */

 

I2c0. i2ccon0 & = ~ (1 <4);/* clear pending condition & resume the operation */
For (delay = 0; delay <0 xFFFF; delay ++ );
Low = i2c0. i2cds0;/* read temperature of Low 1 bit */

I2c0. i2cstat0 & = ~ (1 <5);/* stop signal generation, free bus */
I2c0. i2ccon0 & = ~ (1 <4);/* clean interrup pending bit */
Return (high <8) | low );
}

Int main ()
{
Int temp;
Int low, high;
Uart0_init ();
GPD. gpdcon = (GPD. gpdcon &~ (0x0f <12) | (0x2 <12);/* SDA set GPD [3] functional mode */
GPD. gpdcon = (GPD. gpdcon &~ (0x0f <16) | (0x2 <16);/* SCL set GPD [4] functional mode */

While (1 ){
Temp = set_pointer_and_read_temperature ();
High = temp> 8;
Low = temp & 0xff;
Printf ("Temp is: % d. % d \ n", high, (low> 7) = 0 )? 0: 5 ));
}
Return 0;
}