ARM processor Exception Handling-SWI

This blog on csdn is too well written, so I will repost it to my blog to view it. the following link is the original address of this blog. Thank you for writing lizgo.

Http://blog.csdn.net/lizhiguo0532/archive/2010/10/05/5922639.aspx

 

 

 

The ARM processor has a total of 7 running modes:
User Mode (usr)-normal Program Execution Mode

| -- Fast interrupt mode (FIQ) -- used for high-speed data transmission and Channel Processing

Special | exclusive | external interrupt mode (IRQ) -- used for normal Interrupt Processing
Permission -- | common -- | administrator mode (SVC) -- A protection mode for the operating system
Mode | mode | Data Access stop mode (ABT) -- used for virtual storage and storage protection
| Formula | -- undefined command stop mode (UND) -- used to support coprocessor that simulates hardware through software
| -- System mode (sys) -- used to run privileged Operating System Tasks

Privileged mode: FIQ, IRQ, SVC, Abt, und, and SYS -- the program can access all system resources or switch the processor mode at will.
Exception modes: FIQ, IRQ, SVC, Abt, and und

Arm exception interrupt types and priority:
Priority exception interrupt name
High reset (reset)
| Data abort)
| Fast interrupt request (FIQ)
| External interrupt request (IRQ)
// |/Prefetch abort)
// SWI)
Undefined instruction)

Abnormal vector table:
Priority of address exception interrupt name
..
..
..
0x1c FIQ 3
0x18 IRQ 4
0x14 Reserved x
0x10 Data abort 2
0x0c prefetch abort 4
0x08 SWI 5
0x04 undefined instruction 6
0x00 reset 1
Vector table can be at 0x0 or 0xffff0000 (arm720t, arm9, arm10 ..)
Why do FIQ with priority 3 be placed at address 0x1c? This design was designed to respond to FIQ interruptions more quickly, that is, not at 0x1c.
The address jump command directly stores the most critical FIQ processing code in the address area starting from 0x1c.

Abnormal entry and return:
When an exception occurs:
1. Copy the CPSR value of the current mode to the spsr _ <mode> of the corresponding abnormal mode, for example, CPSR (usr) --> spsr_svc (SVC ).
2. Set the appropriate CPSR bit:
Change processor status to arm status
Change the processor mode to the corresponding exception Mode
If necessary, you can set the interrupt prohibition bit to disable the corresponding interrupt.
3. Save the returned address (pc-4) to LR _ <mode>.
4. Set PC as the corresponding exception vector.
When an exception is returned, you must:
1. Recover CPSR from spsr _ <mode>.
2. Recover a PC from LR _ <mode>
(This return operation can only be performed in the arm status)
Command Analysis for abnormal return:
* Use a data processing command. The command carries the suffix "S" and the PC serves as the destination register.
* In privileged mode, you must not only update the PC, but also copy the spsr to the CPSR.
1. Return exceptions from SWI and UNDEF:
Movs PC, LR
Both of these exceptions will enter an exception in the execution cycle of the command that causes the exception, and will not enter an exception until the next clock cycle, in addition, both exceptions are returned to the next command that generates the exception command to continue execution. I can know from the front that what LR saves is the pc-4 (the Pc value is the address of the next command that generates the exception command), so the LR value can be directly sent to the PC.
2. Return from FIQ, IRQ, and prefect ABORT:
Subs PC, LR, #4
These three exceptions will occur only after the execution of the abnormal command is completed, so the current PC has been updated, for example:
...
Subs R3, R3, #1 <26 @ 0x100
BCS 2B @ 0x104
Subs R1, R1, #1 <5 @ 0x108
BCS 1B @ 0x10b
...
If the preceding three exceptions occur when the 1st line address is 0x100, the current Pc value is 0x108. After the 1st line is executed, the PC is updated to 0x10b. Also go to exception handling, save the LR value as a pc-4 when the exception enters, that is, 0x108. After an exception is returned, if you need to execute the next command that generates the exception command, you must subtract the LR value by 4 to get the correct address, lr-4 = 0x108-4 = 0x104.
3. Data ABORT:
This exception occurs only after the execution of the command that generates the exception is completed. The exception is similar to the three exceptions of the 2nd class, but the difference is: the returned address of a Data Exception is not the next instruction that generates an exception, but the instruction that generates an exception. Therefore, the returned instruction should be:
Subs PC, LR, #8
According to the above example, the execution should be continued at address 0x100. Why is this? Because the data will continue to be retrieved after an exception is returned, think about the page missing exception.
4. If LR is pushed to the stack after an exception occurs, use the following command to bring it up.
Ldmfd SP! , {PC} ^
(^ Copy the spsr to CPSR at the same time. The LR here has done the corresponding processing in the previous 3 before the stack is pressed)

SWI exception:
When you run the SWI Soft Interrupt command, a soft interrupt exception occurs. When a SWI exception occurs, the following actions are performed:
Cspr is saved to spsr_svc.
Change processor status to arm status
Change the processor mode to the corresponding administrator mode (SVC)
Disable interruption.
Save the return address (pc-4) to lr_svc
Set PC to 0x08 or 0xffff0008
** Note: if the system is in SVC mode when the SWI command is executed, the original lr_svc value will be overwritten. So
Before the SWI command, store the lr_svc pressure stack.
When a SWI exception is returned, perform the following actions:
Recover CPSR from spsr_svc
Restores a PC from lr_svc and does not need to be corrected.

Use the keyword "_ SWI" in the C language to define a soft interrupt function:
_ SWI (0x30) void my_swi (void );
Void fun (void)
{
My_swi ();
}
-----> Convert to assembly
Fun
Stmfd SP! , {LR}
SWI 0x24
Ldmfd SP! , {PC}

SWI calls parameters with parameters and SWI processing functions with parameters:
SWI call with parameters:
When using the SWI command, there are usually two methods to pass parameters:
1. Use the SWI number
The SWI command consists of a low 24 bits (arm Instruction Set) or a low 8 bits (thumb Instruction Set) to specify the Soft Interrupt number,
Other parameters are passed through registers.
2. R0 determines the Soft Interrupt number, and other parameters are transmitted using the same register.
** In the C language, the soft interrupt function defined by the keyword "_ SWI" allows a maximum of four parameters, using R0 ~ R4.
SWI processing function with parameters:
1. In the assembly, you can access the registers set by the caller.
2. Pass the parameter to C. Generally, the stack method is used:
Press the parameter stack to pass a pointer to these parameters to the called function.

Obtain the SWI Number:
ARM core does not provide a mechanism to directly transmit Soft Interrupt numbers to the processing program. The SWI processing program must locate the SWI command and extract the constant number field in the SWI command.
1. Check the Tbit of spsr_svc to determine whether the arm instruction set is the thumb instruction set when the command before the SWI exception occurs.
2. Then, determine the address of the SWI command through the lr_svc value. The arm State is the LR-4, while the thumb state is the position of the LR-2.
3. SWI command format:
Arm status:
31 30 29 28 27 26 24 23 22 21 20 19 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
| Cond | 1 1 1 1 | SWI number |
Thumb state
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
| 1 1 0 1 1 1 1 1 1 | SWI number |