ARM processor Exception Handling-SWI

This article Reprinted from: http://blog.csdn.net/lizhiguo0532/article/details/5922639

Thanks very much to the original author!

The ARM processor has a total of 7 running modes:
User Mode (usr)-normal Program Execution Mode

| -- Fast interrupt mode (FIQ) -- used for high-speed data transmission and Channel Processing

Special | exclusive | external interrupt mode (IRQ) -- used for normal Interrupt Processing
Permission -- | common -- | administrator mode (SVC) -- A protection mode for the operating system
Mode | mode | Data Access stop mode (ABT) -- used for virtual storage and storage protection
| Formula | -- undefined command stop mode (UND) -- used to support coprocessor that simulates hardware through software
| -- System mode (sys) -- used to run privileged Operating System Tasks

Privileged mode: FIQ, IRQ, SVC, Abt, und, and SYS -- the program can access all system resources or switch the processor mode at will.
Exception modes: FIQ, IRQ, SVC, Abt, and und

Arm exception interrupt types and priority:
Priority exception interrupt name
High reset (reset)
| Data abort)
| Fast interrupt request (FIQ)
| External interrupt request (IRQ)
// |/Prefetch abort)
// SWI)
Undefined instruction)

Abnormal vector table:
Priority of address exception interrupt name
..
..
..
0x1c FIQ 3
0x18 IRQ 4
0x14 Reserved x
0x10 Data abort 2
0x0c prefetch abort 4
0x08 SWI 5
0x04 undefined instruction 6
0x00 reset 1
Vector table can be at 0x0 or 0xffff0000 (arm720t, arm9, arm10 ..)
Why do FIQ with priority 3 be placed at address 0x1c? This design was designed to respond to FIQ interruptions more quickly, that is, not at 0x1c.
The address jump command directly stores the most critical FIQ processing code in the address area starting from 0x1c.

Abnormal entry and return:
When an exception occurs:
1. Copy the CPSR value of the current mode to the spsr _ <mode> of the corresponding abnormal mode, for example, CPSR (usr) --> spsr_svc (SVC ).
2. Set the appropriate CPSR bit:
Change processor status to arm status
Change the processor mode to the corresponding exception Mode
If necessary, you can set the interrupt prohibition bit to disable the corresponding interrupt.
3. Save the returned address (pc-4) to LR _ <mode>.
4. Set PC as the corresponding exception vector.
When an exception is returned, you must:
1. Recover CPSR from spsr _ <mode>.
2. Recover a PC from LR _ <mode>
(This return operation can only be performed in the arm status)
Command Analysis for abnormal return:
* Use a data processing command. The command carries the suffix "S" and the PC serves as the destination register.
* In privileged mode, you must not only update the PC, but also copy the spsr to the CPSR.
1. Return exceptions from SWI and UNDEF:
Movs PC