Assembly Register function

http//bbs.886520.com/forum-28-1.htmlESP is the stack pointer ebp is the base address pointer 4 data registers (EAX, EBX, ECX, and EDX) 2 variable address and pointer register (ESI and EDI) 2 pointer registers (ESP and EBP) 6 segment Registers (ES, CS, SS, DS, FS, and GS) 1 instruction Pointer Register (EIP) 1 flag Register (eflags)1, the data register data register is mainly used to save the operand and the result of the operation and so on, so as to save the time of the bus and access memory for the read operation. The 32-bit CPU has 4 general-purpose registers of 32-bit eax, EBX, ECX, and edx. Access to low 16-bit data does not affect data that is 16 bits high. These low 16-bit registers are named: AX, BX, CX, and DX, which match the registers in the previous CPU. 4 16-bit registers can be divided into 8 independent 8-bit registers (Ax:ah-al, BX:BH-BL, CX:CH-CL, DX:DH-DL), each register has its own name and can be accessed independently. Programmers can use this "can-be-fit" feature of data registers to flexibly handle words/bytes of information. Registers Ax and Al are often called accumulators (accumulator), and operations with accumulators may take less time. Accumulator can be used to multiply, divide, enter/output and other operations, they are used very frequently, register BX is called base register. It can be used as a memory pointer, and the register CX is called the Count register. In the loop and string operation, it is used to control the number of cycles; In a bitwise operation, when moving multiple bits, CL is used to indicate the number of bits shifted, and the register DX is called the data register. It can be used as the default operand in the multiplication and addition operations, and can also be applied to store I/O's port address. In a 16-bit CPU, AX, BX, CX, and DX cannot hold the address of a storage unit as a base address and a variable address register, but in a 32-bit CPU, its 32-bit registers eax, EBX, ECX, and edx can not only transmit data, hold data from scratch, but also act as a pointer register. Therefore, these 32-bit registers are more versatile. 2, the variable address register 32-bit CPU has 2 32-bit general-purpose registers ESI and EDI. Its low 16 bits correspond to Si and di in the previous CPU, and access to low 16 bits of data does not affect high 16 bits of data. Registers esi, EDI, Si, and di are referred to as the variable-address registers (Index register), which are mainly used to store the offset of the memory cells in the segment, and they can be used to address multiple memory operands to facilitate access to the storage unit in different addresses. The variable address register is not divisible into 8-bit registers. As a general register, the operands and results of arithmetic logic operations can also be stored. They can be used as a general memory pointer. During the execution of the string manipulation instructions, they have specific requirements, and they also have special functions. 3, the pointer register 32-bit CPU has 2 32-bit general-purpose registers EBP and esp. Its low 16 bits correspond to the SBP and SP in the previous CPU, and access to low 16-bit data does not affect the high 16-bit data. Register EBP, ESP, BP, and SP, called the Pointer Register (Pointer register), are mainly used to store the offset of the storage unit in the stack, and they can be used to address multiple memory operands to provide convenient access to the storage unit in different addresses. The pointer register is not divisible into 8-bit registers. As a general register, the operands and results of arithmetic logic operations can also be stored. They are mainly used to access the storage unit in the stack, and it is stipulated that BP is the base pointer (base Pointer) register, which can directly access the data in the stack, and the SP is the stack pointer (stacks Pointer) register, which can only access the top of the stack. 4, segment register segment registers are set according to the management mode of memory fragmentation. The physical address of the memory unit is composed of the value of the segment register and an offset, which can be combined into a memory address that accesses a larger physical space with a value of two less digits. Segment register inside CPU: cs--code Segment Register, whose value is the segment value of the code snippet, the ds--segment register (data Segment register) whose value is the segment value of the data segment; es--Additional segment Register ( Extra Segment Register), whose value is the segment value of the additional data segment, the ss--stack segment register (Stacks Segment register), whose value is the segment value of the stack segment, and the fs--additional segment register (Extra Segment register), The value is the segment value of the additional data segment, and the gs--additional segment register (Extra Segment register), whose value is the segment value of the additional data segment. In a 16-bit CPU system, it has only 4 segment registers, so the program can be accessed directly at most 4 segments in use at any time, and in a 32-bit microcomputer system it has 6 segment registers, so programs developed in this environment can access up to 6 segments at the same time. 32-bit CPUs have two different ways of working: real-mode and protection. In each of these ways, the function of the segment register is different. The provisions are briefly described as follows: Real mode: The first 4 segment registers CS, DS, ES, and SS are exactly the same meaning as the corresponding segment registers in the previous CPU, and the logical address of the memory unit is still the form of "segment value: Offset". To access data within a memory segment, the offset of the segment register and the storage unit must be used. Protection mode: In this way, the situation is much more complex, the loading segment register is no longer a segment value, but a value called "Selector". 5, the instruction pointer register 32-bit CPU extends the instruction pointer to 32 bits, and the lower 16 bits of the EIP,EIP are the same as the IP in the previous CPU. The instruction Pointer Eip, IP (instruction Pointer) is the offset of the code snippet that holds the next instruction to be executed. In a system with prefetch instruction functionality, the next instruction to be executed is usually pre-provisioned to the instruction queue, unless a transfer situation occurs. Therefore, when you understand their functionality, there is no case of instruction queuing. In real mode, since the maximum range for each segment is 64K, the high 16 bits in the EIP are definitely 0, which is equivalent to using only their low 16 bits of IP to reflect the order in which the instructions in the program are executed. 6, Flag register one, operation result flag bit1, carry flag CF (Carry flag) carry Mark CF is mainly used to reflect whether the operation produces carry or borrow. If the highest bit of the result of the operation produces a carry or borrow, its value is 1, otherwise its value is 0. The use of this flag bit is: the addition and subtraction of the number of characters (bytes), the size of the unsigned number comparison operation, the shift operation, the word (byte) between the shift, specifically change the CF value of the instructions. 2, Parity Mark PF (Parity flag) parity Mark PF is used to reflect the results of the operation "1The parity of the number of ″. If1The number of ″ is even, the value of PF is 1, otherwise its value is 0. The PF can be used for parity checking, or for generating parity bits. In the process of data transmission, in order to provide the reliability of the transmission, if the use of parity method, you can use the flag bit. 3, auxiliary carry Flag AF (auxiliary Carry flag) The value of the secondary carry Flag AF is set to 1 if the following occurs, otherwise its value is 0: (1), in the word operation, occurs when a low byte is rounded to a high byte or borrow;2), when the byte operation occurs when the low 4-bit high 4-bit carry or borrow. For the above 6 operation result flag bits, in the general programming case, the use frequency of the flag bit CF, ZF, SF and of is higher, while the use frequency of the flag bit PF and AF is low. 4, 0 Mark ZF (Zero flag) 0 Mark ZF is used to reflect whether the result of the operation is 0. If the result of the operation is 0, its value is 1, otherwise its value is 0. This flag bit can be used when judging whether the result of the operation is 0 o'clock. 5Symbol SF (sign flag ) symbol SF is used to reflect the sign bit of the result of the operation, which is the same as the highest bit of the result. In the microcomputer system, the signed number uses the complement notation, so the SF also reflects the positive and negative sign of the result of the operation. When the result of the operation is positive, the SF value is 0, otherwise its value is 1. 6, the overflow flag of the (Overflow flag) overflow flag is used to reflect whether the result of a signed number plus minus operation overflows. If the result of the operation exceeds the range that can be represented by the current number of operations, it is called overflow, and the value of of is set to 1, otherwise the value of of is cleared to 0. "Overflow" and "carry" are two different meanings of the concept, do not confuse. If you're not sure, check out the relevant chapters in the principles of computer composition course. State control flag bit state control flag bits are used to control the CPU operation, they have to pass special instructions to make it change. 1, trace flag tf (TRAP flag) when the trace flag TF is set to 1 o'clock, the CPU goes into single-step execution, that is, each execution of an instruction, resulting in a single-step interrupt request. This method is mainly used for program debugging. There is no specific instruction in the instruction system to change the value of the flag bit TF, but the programmer can use other methods to change its value. 2, interrupt allow flag if (interrupt-enable flag) interrupt allow flags if is used to determine whether the CPU responds to interrupt requests made by a masked interrupt outside the CPU. However, regardless of the value of the flag, the CPU must respond to an interrupt request from an unshielded interrupt outside the CPU, as well as an interrupt request that is generated internally by the CPU. Specific provisions are as follows: (1), when if=1 o'clock, the CPU can respond to interrupt requests made by a masked interrupt outside the CPU;2), when if=0 o'clock, the CPU does not respond to interrupt requests made by a masked interrupt outside the CPU. The instruction system of the CPU also has special instructions to change the value of the flag bit if. 3, Direction flag df (Direction flag) Direction Mark DF is used to determine the direction of the pointer register adjustment when the string operation instruction executes. Specific provisions in 5th.2. Section 11--String manipulation instructions--is given in. In the instruction system of microcomputer, a special instruction is provided to change the value of the flag bit DF. Three, 32-bit flag register increased flag bit1, I/O privilege flag IOPL (i/O Privilege level) IThe/O privilege flag is represented by a two-bit bits, also known as an I/O privilege level field. This field specifies the privilege level that requires the execution of I/O directives. If the current privilege level is less than or equal to the value of IOPL, then the i/o instruction is executable, otherwise a protection exception will occur. 2, nested Task Flags NT (Nested Task) nested task flags NT is used to control the execution of the interrupt return instruction Iret. Specific provisions are as follows: (1), when nt=0, restore EFlags, CS, and EIP with the values saved in the stack, and perform a regular interrupt return operation;2), when nt=1to implement interrupt return through task transformation. 3, restart flag RF (Restart flag) Restart flag The RF is used to control whether to accept debug failure. Regulation: RF=0 o'clock, which means "accept" debug failure, otherwise reject it. After a successful execution of an instruction, the processor set the RF to 0, and when it accepts a non-debug fault, the processor will set it to 1. 4, virtual 8086-way flag VM8086mode) If the value of this flag is 1, the processor is in a virtual 8086 mode of operation, otherwise, the processor is in a general protection mode of operation. 

Assembly Register function