Asynchronous clock FIFO (one)

FIFO is typically used for data transmission over two different clock domains. A pool has two channels in and out, and it needs to be cushioned because of inconsistent inlet and outlet flow. The stack is also the equivalent of a pool. If the input is not a continuous stream of data, the stack can be used to adjust the output of the data to a stable state. If the input clock of the data is greater than the output, then there is always a time when the stack overflows and this part of the overflow is discarded. General asynchronous clocks need to be synchronized, this article is only based on the FIFO basic principles of programming. The FIFO will be technically improved in the future.

Code:

1Module Fifio (Input clkin,input write,input [7:0] Datain,input clkout,input read,output reg [7:0] Dataout,output reg empty,output reg full);2reg [7:0]stack[16383:0];3reg [9:0]data_in_point=0;4reg [Ten:0] Data_in_count=0;5reg [Ten:0]data_out_point=0;6Reg data_in_num=0;7Reg data_out_num=0;8 [email protected] (Posedge Clkin)9 beginTen              One                          Case(Data_in_num) A                             0:if(write) Beginif((Data_in_count-data_out_point) >Ten'h3fff) begin full<=1;data_in_num<=0;end Else begin data_in_point<=data_in_count[9:0];d ata_in_num<=1 ; Full<=0;end End -                             1: Begin stack[data_in_point]<=datain;data_in_count<=data_in_count+1;d ata_in_num<=0; end - Endcase the  - End - [email protected] (Posedge clkout) - begin +      -                      Case(Data_out_num) +                         0:if(read) BEGINif((data_in_count-data_out_point) = =0) Begin empty<=1;d ata_out_num<=0; endElseBegin empty<=0;d ata_out_num<=1; end End A                         1: Begin Dataout<=stack[data_out_point];d ata_out_num<=0;if(data_out_point==Ten'h3fff) Data_out_point<=0;else data_out_point<=data_out_point+1; End at Endcase -          - End -  -Endmodule

Verification Code:

1 module Fifibench ();2 reg Clkin,clkout;3 reg Write,read;4 Wire empty,full;5Wire [7:0]dataout;6reg [7:0] DataIn;7 Fifio M0 (. Clkin (Clkin),. Write (write),. DataIn (DataIn),. Clkout (Clkout),. Read (read),. Dataout (Dataout),. Empty ( Empty),. full);8Initial begin clkin=0; clkout=0; write=0; read=0;d atain=0; end9Always begin #2clkin=!Clkin;endTenAlways begin # -clkout=!Clkout;end OneAlways begin # -write=!Write;end AAlways begin # -read=!Read;end -Always begin # +datain=datain+1; end -Initial #10000$stop; theEndmodule

Asynchronous clock FIFO (one)