Bare metal DMA

/*************************************** **************************************** * ****************************** File Name: DMA. C * function: Base DMA driver function * Author: cp1300@139.com * Creation Time: January 23, 2013 * last modification time: January 23, 2013 * Details: the underlying driver of the DMA controller is ************************************ **************************************** * *******************************/# include "system. H "# include" DMA. H "/***************************** **************************************** **************************************** * ************ Function: void dma_init (void) * function: DMA initialization * parameter: No * returned: No * dependency: underlying * Author: cp1300@139.com * Time: 20130131 * last modification time: 20130131 * Note: no *************************************** **************************************** **************************************** **/void dma_init (void) {set_gateclk (hclk_dma0, enable); set_gateclk (hclk_dma1, enab Le );} /*************************************** **************************************** **************************************** * ** function: void dma_setconfig (dma_typedef * DMA, dma_chx CH, dma_config * config) * function: DMA configuration * parameter: DMA module selection, see dma_typedef; Ch: channel selection, see dma_chx; config: configuration, see dma_config * returned: No * dependency: underlying * Author: cp1300@139.com * Time: 20130131 * last modification time: 20130131 * description: used to set DMA ************************************* ************ **************************************** * ******************************/Void dma_setconfig (dma_typedef * DMA, dma_chx CH, dma_config * config) {dma_enable (DMA); // enable the DMA module (DMA-> CH [CH]). srcaddr = config-> srcaddr; // set the source address (DMA-> CH [CH]). destaddr = config-> destaddr; // set the target address (DMA-> CH [CH]). control0 = 0x80000000 // 1 <31 // are there any interruptions after the current transmission is completed | (config-> destincrement = Enable )? (1 <27): 0) // auto-increment target address | (config-> srcincrement = Enable )? (1 <26): 0) // Source Address Auto-increment | (config-> destperipheral = dma_mem )? Ahb_m1: ahb_m2) <25 // select the target AHB host | (config-> srcperipheral = dma_mem )? Ahb_m1: ahb_m2) <24 // source AHB host selection | (config-> flowwidth & 0x7) <21 // target transmission width | (config-> flowwidth & 0x7) <18 // source transmission width | (config-> burstsize & 0x7) <15 // target transmission pulse size, quantity of individual transmissions | (config-> burstsize & 0x7) <12; // source transmission pulse size, the number of data transmitted at a time (DMA-> CH [CH]). control1 = config-> datasize & 0x1ffffff; // The number of data transferred (DMA-> CH [CH]). config = (0 <18) // enable DMA requests | (0 <16) // disables locked transfers | (1 <15) // teminal count interrupt Enable | (0 <14) // interrupt error mask // allow DMA requests | (config-> srcperipheral = dma_mem )? 0: 1) <12) | (config-> destperipheral = dma_mem )? 0: 1) <11) // transmission mode, such as memory to memory | (config-> destperipheral & 0x0f) <6 // target peripherals | (config-> srcperipheral & 0x0f) <1; // source peripherals (DMA-> CH [CH]). llI = config-> lliarrd; // configure the location of the next transmission llI // (DMA-> CH [CH]). configexp = 7 ;} /*************************************** **************************************** **************************************** * ** function: void dma_enable (dma_typedef * DMA) * function: DMA enabling * parameter: DMA: select the DMA module. For details, see dma_typedef. * return: No * dependency: underlying * Author: cp1300@139.com * Time: 20130131 * last modification time: 20130131 * description: no *************************************** **************************************** **************************************** **/void dma_enable (dma_typedef * DMA) {DMA-> Config = 0x01; // AHB small-end mode, start the DMA controller }/*********************************** **************************************** **************************************** * ****** function: void dma_disable (Dma_typedef * DMA) * function: DMA off * parameter: DMA module selection, see dma_typedef; * return: No * dependency: underlying * Author: cp1300@139.com * Time: 20130131 * last modification time: 20130131 * description: no *************************************** **************************************** **************************************** **/void dma_disable (dma_typedef * DMA) {DMA-> Config = 0x00; // AHB small-end mode, disable the DMA controller }/*********************************** **************************************** ***** **************************************** ** Function: void dma_startchannels (dma_typedef * DMA, dma_chx ch) * function: DMA Channel Transmission start * parameter: DMA module selection, see dma_typedef; Ch: channel selection, see dma_chx; * return: no * dependency: underlying * Author: cp1300@139.com * Time: 20130131 * last modification time: 20130131 * description: no *************************************** **************************************** **************************************** **/void dma_startchannels (dma_typedef * DMA, dma_chx ch) {Dma_clearinttcstatus (dma0, CH); dma_clearinterrorstatus (dma0, CH); (DMA-> CH [CH]). config | = 1 <0; // channel enabling }/********************************* **************************************** **************************************** * ******** function: void dma_waitcomplete (dma_typedef * DMA, dma_chx ch) * function: Waiting for transmission to complete * parameter: DMA module selection, see dma_typedef; Ch: channel selection, see dma_chx; * return: no * dependency: underlying * Author: cp1300@139.com * Time: 20130131 * Last modified: 2013013 1 * description: no *************************************** **************************************** **************************************** **/void dma_waitcomplete (dma_typedef * DMA, dma_chx ch) {While (! (DMA-> rawinttcstatus & (1 <ch )));} /*************************************** **************************************** **************************************** * ** function: void dma_clearinttcstatus (dma_typedef * DMA, dma_chx ch) * function: Clear DMA transmission completion interrupt status * parameter: DMA: select the DMA module, see dma_typedef; Ch: select a channel, see dma_chx; * return: No * dependency: underlying * Author: cp1300@139.com * Time: 20130131 * last modification time: 20130131 * Note: no *************************************** **************************************** **************************************** **/void dma_clearinttcstatus (dma_typedef * DMA, dma_chx ch) {DMA-> inttcclear | = 1 <ch ;} /*************************************** **************************************** **************************************** * ** function: void dma_clearinterrorstatus (dma_typedef * DMA, dma_chx ch) * function: Clear DMA Transmission Error interrupt status * parameter: DMA: select the DMA module, see dma_typedef; Ch: select a channel, see dma_chx; * return: No * dependency: underlying * Author: cp1300@139.com * Time: 20130131 * last modification time: 20130131 * Note: no *************************************** **************************************** **************************************** **/void dma_clearinterrorstatus (dma_typedef * DMA, dma_chx ch) {DMA-> interrclear | = 1 <ch ;}

# Ifndef dma_h _ # define dma_h _ // The DMA channel defines typedef Enum {dma_ch0 = 0, dma_1_= 1, dma_ch2 = 2, dma_ch3 = 3, dma_ch = 4, limit = 5, records = 6, records = 7,} dma_chx; // DMA separate channel structure typedef volatile struct {vu32srcaddr; role; vu32lli; vu32control0; vu32control1; vu32config; vu32configexp; vu32reserved;} role; // DMA register structure typedef volatile struct {vu32intstatus; // interrupt status vu32inttcstatus; // The interrupt status vu32inttcclear during processing; // The interrupt clearing vu32 interro Rstatus; vu32interrclear; empty; vu32softbreq; vu32softsreq; vu32softlbreq; empty; vu32config; vu32sync; vu32reserved [50]; // retain dma_ch_config ch [8]; // eight independent channels} dma_typedef; // base address of the four DMA controllers # define register # define dma1_base0x75100000 # define register // DMA register pointer # define dma0 (dma_typedef *) dma0_base) # define dma1 ((Dma_typedef *) dma1_base) # define sdma0 (dma_typedef *) sdma0_base) # define sdma1 (dma_typedef *) sdma1_base) // The DMA source defines typedef Enum {// dma0, sdma0dma_mem = 0, priority = 0, dma_uart0_1 = 1, dma_uart1_0 = 2, dma_uart1_1 = 3, priority = 4, priority = 5, priority = 6, dma_uart3_1 = 7, priority = 8, dma_pcm0_rx = 9, expires = 10, expires = 11, dma_spi0_tx = 12, dma_spi0_rx = 13, dma_hsi_tx = 14, dma_hsi_rx = 15, // dma1, expires = 16, dma_pcm1_rx = 17, expires = 18, expires = 19, dma_spi1_tx = 20, dma_spi1_rx = 21, expires = 22, dma_ac_pcmin = 23, dma_ac_micin = 24, dma_pwm = 25, dma_irda = 26, dma_secu_rx = 30, dma_secu_tx = 31} dma_sources_type; // DMA transmission type definition/* typedef Enum {memtomem = 0, // memory to memory memtoper = 1, // memory to peripherals pertomem = 2, // peripherals to memory pertoper = 3 // peripherals to peripherals} dma_transfer_type; */typedef Enum {no_int_pend = 0x0, tc_int_pend = 0x1, err_int_pend = 0x2, Tc_and_err_int_pend = 0x3} dma_int_status; // type typedef Enum {ahb_m1 = 0, // AHB host 1ahb_m2 = 1, // AHB host 2} dma_ahb_type; // dam transmission width: typedef Enum {width_8bit = 0, // 8bitwidth_16bit = 1, // 16bitwidth_32bit = 2 // 32bit} dam_width_type; // source or target burst transmission size: typedef Enum {burst1 = 0, burst4 = 1, burst8 = 2, burst16 = 4, burst32 = 5, burst64 = 6, burst128 = 7, burst256 = 8} dma_burstsize_type;/** four-character FIFO of each channel in DMAc. Therefore, the pulse string size and transmission width are limited by the FIFO size. For example, if the data width is word, the available burst pulse size is 4. If the data width is byte, the burst size is less than 16 years old. * // DMA transmission configuration typedef struct {u32srcaddr; // DMA source address u32destaddr; // dam target address direction; // source peripherals dma_sources_typedestperipheral; // target peripherals functionalstatesrcincrement; // source address incremental mode functionalstatedestincrement; // target address incremental mode dam_width_typeflowwidth; // transmission width ize; // burst transmission size u32datasize; // Number of transmitted data, 32bitu32lliarrd; // next transmission configuration address} dma_config; // set typedef struct {u32srcaddr; // The Source Address u32destaddr of the next transmission; // the destination address u32lliaddr of the next transmission; // The llI address of the next transmission u32dmacontrol0; // The dmacontrol0 data u32dmacontrol1 of the next transmission; // The dmacontrol1 data of the next transmission} dma_lli_addr; // function declaration void dma_init (void ); void dma_setconfig (dma_typedef * DMA, latency CH, dma_config * config); void Merge (dma_typedef * DMA); void dma_disable (dma_typedef * DMA); void Merge (dma_typedef * DMA, dma_chx ch); void Merge (dma_typedef * DMA, dma_chx ch ); # endif/* dma_h _*/