Basic arm Development Board knowledge

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1. Some common abbreviations and explanations of ARM

MSB: the highest valid bit;
LSB: minimum valid bit;
AHB: advanced high-performance bus;
VPB: a large-scale peripheral bus connecting the peripheral functions of the chip;
EMC: external memory controller;
Mam: Memory acceleration module;
VIC: vector interrupt controller;
SPI: full-duplex serial interface;
Can: controller LAN, a serial communication protocol;
PWM: pulse width modulation;
TM: Embedded tracking macro;
CPSR: Current Program Status Register;
Spsr: Program protection status register;

2. Precautions for using-Mam in arm:

A: When changing the scheduled mam value, you must first disable MAM by writing 0 to mamcr, and then write the new value to mamtim. Finally, write the value of the required operation mode to mamcr and enable mam again.
For a system clock below 20 MHz, mamtim is set to 001. For a system clock between 20 MHz and 40 MHz, we recommend that you set the flash access time to 2 cclk. For a system clock above 40 MHz, we recommend that you use 3 cclk.

3. Precautions for using-Vic in arm

A:
If the code is run in the On-chip RAM and the application needs to call the interrupt, the interrupt vector must be re-mapped to the flash Address 0x0. This is done because all the abnormal vectors are located at the address.
0x0 and above. This is achieved by configuring the register memmap (in the system control module) to the user Ram mode. User code is connected to enable the interrupted vector table to be loaded
0X4000 0000.

4. Arm startup code design in arm

A: The arm startup code is used to program the processor kernel and hardware controller. assembly languages are generally used. The startup Code generally includes:
Interrupt vector table
Initialize the Storage System
Initialize the ports and devices with special requirements for Stack Initialization
Initialize the user program execution environment
Change processor Mode
Call the main application

5. Differences between-IRQ and Fiq in arm

A: IRQ and FIQ are arm processors.
Of
Two programming modes. IRQ refers to the interrupt mode, while FIR refers to the fast interrupt mode. For FIQ, you must handle your tasks as soon as possible and leave this mode.
IRQ can be interrupted by FIQ, but IRQ cannot be interrupted by FIQ. To make FIQ faster, more shadow registers are available in this mode. FIQ cannot call SWI (soft
Parts are interrupted ). FIQ must also disable interruption. If a FIQ routine must re-enable interrupt, it is too slow and should be IRQ rather than FIQ.

6.-Arm processors in arm
Response Process to abnormal interruptions

Answer: ARM processor
The Response Process for abnormal interruptions is described as follows:
Saves the current status of the processor, the interrupt shielding bit, and the flag of each condition;
Set the corresponding bits in the CPSR of the current program status register;
Set the registers lr_mode to the return address;
Set the program counter value PC to the interrupt vector address of the exception interrupt and jump to the corresponding exception interrupt for execution.

7. Differences between the-arm instruction and the thumb instruction in arm

A:
In the ARM architecture, the instruction set in the arm instruction set contains 32-bit instructions, which are highly efficient. For a 16-bit application system with a storage system data bus, the arm system provides the thumb command
Set. The thumb instruction set is re-encoded from a subset of the arm instruction set. The instruction set length is 16 bits. Generally, when a processor executes an arm program, the processor is in the arm state.
During the Thumb program, the processor is in the thumb state. The thumb instruction set does not change the programming model of the arm system, but adds some constraints to the model.
The operations of data processing commands in the thumb instruction set are still 32-bit, and the instruction addressing address is also 32-bit.

8. What is atpcs in arm?

A: To enable mutual calls between separately compiled C and assembler programs, certain rules must be specified for calls between subprograms. Atpcs are the basic rules for ARM program and Thumb program neutron program calls. These rules include register usage rules, data stack usage rules, and parameter transfer rules.

9. Hybrid use of the-arm program and the Thumb program in arm

A: Generally, thumb programs are more compact than arm programs, and thumb programs are more efficient for systems with 8-bit or 16-Bit Memory. However, in the following scenarios, the program must run in the arm State. In this case, you need to mix the arm and thumb programs.
Arm programs should be used to emphasize speed;
Some functions can only be completed by arm programs. For example, use or prohibit abnormal interruptions;
When the processor enters the abnormal Interrupt Processing Program, the program State switches to the arm state, that is, some commands at the entrance of the exception Interrupt Processing Program are arm commands, and then the program can switch to the thumb state as needed, before the program returns an exception interrupt, the program switches to the arm state.
ARM processor
Always starts from the arm status. Therefore, to run the Thumb program in the debugger, you must add an arm program header for the Thumb program, switch to the thumb state, and execute the Thumb program.

10.-Arm processors in arm
Running Mode

Answer: ARM microprocessor
Seven running modes are supported:
User Mode (usr): ARM processor
Normal program execution status;
Fast interrupt mode (FIQ): used for high-speed data transmission or channel management;
External Interrupt mode (IRQ): used for general interrupt processing;
Management Mode (SVC): The protection mode used by the operating system;
Data Access termination mode (ABT): This mode is used to protect virtual storage and storage when data or command prefetch is terminated;
System Mode (sys): Run privileged operating system tasks;
Undefined command stop mode (UND): This mode is used to support software simulation of hardware coprocessor when undefined commands are executed.

11. Exception types supported by the-ARM architecture in arm

A: The exceptions and meanings supported by the ARM architecture are as follows (the number in the circle indicates the priority ):
Reset ①: When the reset level of the processor is valid, a reset exception occurs, and the program jumps to the reset exception for execution (exception vector: 0 X );
Undefined instruction 6: When the ARM processor
Or a definition exception occurs when the coprocessor encounters an instruction that cannot be processed. This exception mechanism can be used for Software Simulation (exception vector: 0 X );
Software interruption 6: a swi command is generated and can be used to call privileged operation commands in user mode. You can use this exception mechanism to call system functions (exception vectors: 0 x );
Command prefetch abort ⑤: If the prefetch instruction address of the processor does not exist or the address does not allow access of the current instruction, the memory sends a abort signal to the processor. When the prefetch instruction is executed, command prefetch abort exception (exception vector: 0x0000,000 C );
Data abort ②: If the IP address of the Instruction for accessing the processor data does not exist or the IP address does not allow access to the current instruction, an exception occurs (exception vector: 0 x );
IRQ ④ (external interrupt request): an IRQ exception occurs when the processor's external interrupt request pin is valid and the I-bit in CPSR is 0. The system Peripherals can interrupt the service with this exception request (exception vector: 0 X );
FIQ ③ (fast interrupt request): When the processor's fast interrupt request pin is valid and the F bit in CPSR is 0, a FIQ exception is generated (exception vector: 0x0000,001 C ).
Note: The exception Vector 0x0000,001 4 is the reserved exception vector.

12. Memory Format of the-ARM architecture in arm

A: The Memory Format of the ARM architecture is as follows:
Large-end format: the high bytes of word data are stored in the low address, and the low bytes of word data are stored in the high address;
Small-end format: In contrast to the large-end storage format, the high-address stores the high bytes of data, and the low-address stores the low bytes of data.

13. Arm register Summary
:
Arm has 16 32-bit registers (R0 to R15 ).
R15 acts as the program register PC, R14 (link register) stores the return address of the subroutine, and R13 stores the stack address.
Arm has a current Program Status Register: CPSR.
Some registers (R13, R14) generate new instances when an exception occurs, such as the IRQ processor mode. In this case, the processor uses r13_irq and r14_irq.
Arm's subroutine calls are fast, because the return address of the subroutine does not need to be stored in the stack.

14. Reasons for memory re ing in arm:

Enable the FIQ handler in flash memory to avoid memory boundary issues caused by re ing;
The use of the SRAM and boot block vectors used to process the middle section of the Code space boundary arbitration is greatly reduced;
Provides space for Jump beyond the range of Single-word transfer commands to save constants.

15. Why the program jumps to the exception vector table using the LDR command instead of the B command:
The LDR command can jump to the full address range, while the B command can only jump to the front and back 32 MB;
The chip has the remap function. When the vector table is in internal RAM or external memory, the B command cannot be used to jump to the correct position.

16. Key Points of-PLL in arm:

The PLL is disabled and bypassed when the chip is reset or enters the power-down mode. The PLL setting will not be automatically restored after the power-down is awakened;
PLL can only be enabled through software;
After being activated, the PLL must wait for it to be locked before it can be connected;
If the PLL is improperly set, the chip may be incorrectly operated.

17. Differences between ARM-and arm:

The ARM7 kernel is a three-level assembly line of 0.9 MIPS/MHz and a Von nuoman structure. The ARM9 kernel is a five-level assembly line that provides a 1.1 MIPS/MHz Harvard structure.
Arm720t is MMU; arm940t is only memory Protection Unit. It is not a complete MMU.
ARM7TDMI provides excellent performance-power consumption ratio. It contains the kernel of thumb instruction set fast multiplication instruction and ice debugging technology. The clock frequency of arm9is higher than that of arm7. it uses the Harvard structure to distinguish between the data bus and the command bus.

18. The basic operations of-Vic in arm are as follows:

A:
Set IRQ/FIQ interruption. If IRQ is interrupted, you can set it to vector interrupt and assign the interrupt priority. Otherwise, it is not a vector IRQ. Then, you can set the allowable interrupt and the corresponding URL or non-directed vector interrupt.
Default address of volume interruption. If an IRQ interrupt occurs, you can read the vector address register and jump to the corresponding code. When you want to exit the interrupt, write 0 to the vector address register to notify the vic to interrupt.
End. When an interruption occurs, the processor switches the processor mode and the related registers are mapped.

19. Use External Interrupt
After a pin is set to the external interrupt function, the pin is in the input mode. Because there is no internal pull-up resistor, an external pull-up resistor is required to ensure that the PIN is not suspended;
In addition to setting the pin connection module, you also need to set the vic module to generate an External Interrupt. Otherwise, the External Interrupt can only be reflected in the extint register;
To enable the device to enter the power-down mode and wake up through external interruptions, the software should correctly set the pin's external interrupt function before entering the power-down mode.

20. Basic uart0 operations
Set I/O to connect to uart0;
Set the serial port baud rate (u0dlm, u0dll );
Set the serial port working mode (u0lcr, u0fcr );
Send or receive data (u0thr, u0rbr );
Check the serial port status or wait for the serial port to be interrupted (u0lsr ).

21. Basic I2C operations
Answer: The basic operation method of the I2C host is as follows:
Set I2C pin connection;
Set I2C clock rate (i2sclh, i2scll );
Set as host, and send the start signal (i2en, Stas, and AA are 0 in i2conset );
The sending slave address (i2dat) controls the i2conset sending;
Determines the bus status (i2stat) for data transmission control;
Sending end signal (i2conset ).
Basic I2C slave operation method:
Set I2C pin connection;
Set its own slave address (i2adr );
Enable I2C (i2en and AA bits of i2conset are 1 );
Determine the SI bit or wait for I2C interruption and wait for host operation;
Determines the bus status i2stat for data transmission control.

22. Arm-PWM basic operation method:

Connect the PWM function pin output, that is, set pinsel0 and pinsel1;
Set the PWM timer's clock frequency division value (pwpr) to obtain the desired timer clock;
Set the Compare match control (pwmmcr), and set the corresponding compare value (pwmmrx );
Set the PWM output mode and allow PWM output (pwmpcr) and locking enable control (pwmler );
Set pwmtcr, start the timer, and enable PWM;
When you want to change the comparison value during running, you need to set the lock enabling function after the change.
We recommend that pwm2, pwm4, and pwm6 be used for bilateral along-PWM output. When single-side PWM output is used, it is high at the beginning of the PWM period and low after matching, pwmmr0 is used as the PWM cycle control and pwmmrx is used as the duty cycle control.