Basic arm knowledge

** 31 General registers, including program counters (PCS. These registers are all 32-bit registers.

** Six status registers. These registers are all 32-bit registers.

ARM processorThere are 7 different processor modes, each of which has a set of corresponding register groups. Visible registers include 15 General registers (R0-R14), one or two State registers and program counters (PC) at any time ). Some of the registers share one physical Register in each mode, and some have their own independent physical registers in each mode.

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General registers

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General registers are divided into the following three categories: Backup registers, unbacked registers, program counters PC

Register not backed up

Unbacked registers include R0-R7. For each unbacked register, the same physical register is used in all processor modes. Non-Backup registers are not used by the system for special purposes. Non-Backup registers can be used in any scenarios where general-purpose registers can be used.

Backup register

For R8-R12 backup registers, each register corresponds to two different physical registers. To apply the backup register for any special purpose, The FIQ processor does not have to execute commands to save and recover the interrupt scene when the interrupt processing is very simple and only the R8-R14 register is used, in this way, the interrupt processing can be very fast.

For R13 and R14 backup registers, each register corresponds to six different physical registers, one of which is shared by the system mode and the user mode; the other five correspond to the other five processor modes. The following mark is used to differentiate physical registers:

R13 _ <mode>

Mode can be one of the following modes: USR, SVC, Abt, und, IRQ, FIQ

Program counter PC

It can be used as a general-purpose register, but some commands have some restrictions when using R15. Because arm uses a pipeline processor mechanism, when the Pc value is correctly read, this value adds 8 bytes to the current command address value. That is to say, for the arm instruction set, the PC points to the address of the next two commands of the current command. Since arm commands are word-aligned, The 0th bits of the PC value and the first bits are always 0.

Note that when you use str/STM to save R15, the current command address value may be added to 8 bytes, it may also save 12 bytes of the Current Instruction address value. Which method depends on the specific design of the chip. For users, try to avoid using the str/STM command to save the R15 value.
When a value is successfully written to R15, the program will jump to this address for execution. Since arm commands are word-aligned, the value of R15 written must meet the requirement that BITs [1:0] Is 0b00. The specific requirements for ARM versions are different:
** For arm3 and earlier versions, the bits [1:0] address value written to R15 is ignored. That is, the address value written to R15 is equal to 0 xFFFF fffc.
** For arm4 and later versions, the program must ensure that the bits [1:0] written to R15 is 0b00; otherwise, unpredictable consequences will occur.
For the thumb instruction set, the command is team aligned, and the processor will ignore bit [0].
Arm basics 2
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Program Status Register

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CPSR (current Program Status Register) is accessed in any processor mode. It contains the condition flag bit, the interrupt prohibition bit, the current processor mode mark, and some other control and status bit. Each processor

Each mode has a dedicated physical status register called spsr (backup program status register)
. When a specific exception interrupt occurs, this register is used to store the content of the current program status register. You can use spsr to restore CPSR when an exception is terminated. Because the user mode and system mode are not abnormal

Interrupt mode, so he does not have spsr. When users access spsr in user mode or system mode, unpredictable consequences will occur.
The CPSR format is as follows. The format of spsr is the same as that of CPSR.

31 30 29 28 27 26 7 6 5 4 3 2 1 0
N z C v q DNM (Raz) I f t M4 m3 m2 M1 M0

* ** Condition flag ***
N -- set the base value to the bit [31] value of the current command operation result. For two signed integer operations, n = 1 indicates that the calculation result is negative, and n = 0 indicates that the result is positive or zero.

Z -- Z = 1 indicates that the calculation result is zero. z = 0 indicates that the calculation result is not zero. For CMP commands, Z = 1 indicates that the two numbers for comparison are of the same size.

C -- The following describes how to set C in four cases:
In addition commands (including comparison command CMP), when the result produces carry, c = 1 indicates that the unsigned operation overflows. In other cases, c = 0.
In the subtraction command (including the subtraction command CMP), if the operation is misaligned, c = 0 indicates that the number of unsigned operations overflows. In other cases, c = 1.
For non-alkali operation commands containing shift operations, C contains the value of the last overflow bit.
For other non-addition or subtraction operation commands, the C-bit value is usually not affected.
V-for addition and subtraction operation commands, when the operands and operation results are binary supplementary codes, V = 1 indicates that the symbols are overflow. Generally, other commands do not affect the V bit.

* ** Q flag ***
In the eseries processor of arm V5, the bit [27] of CPSR is called the Q flag, which is mainly used to indicate whether the enhanced DSP command has exceeded. The bit [27] of the same spsr is also called the Q flag, which is used in exceptions.

The Q position in CPSR is saved and restored when the disconnection occurs.
In earlier versions of arm V5 and non-E series Processors of arm V5, Q flag is not defined.

* ** Control bit in CPSR ***

CPSR's low octal I, F, T, and m [] are collectively referred to as control spaces. These bits change when an exception is interrupted. In privileged processor mode, software can modify these control bits.

** Interrupt prohibited bit: IRQ is prohibited when I = 1, and FIQ is disabled when F = 1.

** T control bit: The t control bit is used to control the command execution status, that is, whether the command is an arm command or a thumb command. For arm V4 T series later versionsARM processor, The meaning of the t control bit is as follows:
T = 0 indicates executing the arm command
T = 1 indicates executing the thumb command
For arm V5 and later non-T series Processors, the meaning of the t control bit is as follows:
T = 0 indicates executing the arm command
T = 1 indicates that the next execution of the command is forced to generate an undetermined command interrupt.

* ** M control bit ***
The m control bit control processor mode has the following meanings:

M [] registers accessible in processor Mode
Ob10000 user PC, R14 ~ R0, CPSR
0b10001 fiq pc, R14_FIQ-R8_FIQ, R7 ~ R0, CPSR, spsr_fiq
0b10010 irq pc, R14_IRQ-R13_IRQ, R12 ~ R0, CPSR, spsr_irq
0b10011 supervisor PC, R14_SVC-R13_SVC, R12 ~ R0, CPSR, spsr_svc
0b10111 abort PC, R14_ABT-R13_ABT, R12 ~ R0, CPSR, spsr_abt
0b11011 undefineed PC, R14_UND-R8_UND, R12 ~ R0, CPSR, spsr_und
0b11111 system PC, R14-R0, CPSR (arm V4 and later)

* ** Other bits in CPSR ***

These bits are used for future expansion. Do not operate these bits in the application software.