Basic Method of Time Series Analysis

Introduction to the basic methods of time series analysis (1)
-- Shared Clock System
1. Timing Analysis involves the following basic factors:
Clock cycle tclk
Data Validity Period taccess
Transmission Line latency tflight
Data creation time tsetup
Data Retention Time thold
Clock Deviation tskew
Clock jitter tjitter
Synchronous crosstalk latency tcrosstalk
(As shown in Figure 1: The clock signal is provided by a dedicated clock circuit, and then the benchmark clock is provided for the output device respectively)


Generally, during device communication, data is transmitted once in a clock period. The key point of time sequence requirements can meet the setup time and retention time of the input device under any circumstances, this ensures reliable data transmission.

2. Basic Analysis Methods
(1) data transfer process (for example, 2): assume that the rising edge of the clock at T1 triggers the output circuit of the output device to start outputting data, after taccess time data appears on the Data Bus and becomes stable, it then goes through tflight +/-tskew +/-tjitter +/-tcrosstalk time to reach the pin of the input device, at the time of T2, that is, the next time when the clock is rising, the input circuit is triggered to sample the data on the data bus to the internal circuit. At the time of T2, the output circuit of the output device starts the next data transmission, in this way, data is transmitted repeatedly.
(2) PCB cabling length requirements Calculation
In PCB design, we generally need two reference values: the maximum latency and the minimum latency of the cabling. The worst case is taken into consideration during analysis. The maximum value of each time period is shown in 3:
Two equations can be obtained:
Taccess_max + tfight +/-tskew +/-tjitter +/-tcrosstalk + tsetup = tclk taccess_min + tfight +/-tskew +/-tjitter +/-tcrosstalk = thold
You can get: tsetup = Tclk-Taccess_max-Tfight +/-tskew +/-tjitter +/-tcrosstalk
The setup and retention time of the input device should be met at any time:
Tsetup> tsetup_min
Thold> thold_min
The PCB latency requirements can be obtained from the above formulas (that is, the timing calculation formula of the common clock system ):
Tflight_max <TCLK-TACCESS_MAX-TSKEW-TJITTER-TCROSSTALK-TSETUP_MIN
Tfight_min> Thold_min-Taccess_min + tskew + tjitter + tcrosstalk

Note: several parameters in the above formula can be found in the device manual.