Brief understanding of Tony's I2C Protocol

I. Technical Performance:

The working rate can be K or K;

Supports multi-host communication;

Multiple master control modules are supported, but only one master is allowed at a time;

A Serial Bus consisting of a data line SDA and a clock SCL;

Each circuit and module has a unique address;

Each device can use an independent power supply, but must

Ii. basic working principle:

The start signal is used to take charge of the bus, and the stop signal is used to release the bus;

Each communication starts with start and ends with stop;

After the start signal is enabled, an address byte is sent, 7 of which are the address code of the controlled device, and 1 is the read/write control bit R/W, R. if the value of W is 0, data is written from the master to the controlled device. If the value of R/W is 1, data is read from the master to the controlled device;

When the controlled device detects that the received address is the same as its own address, it returns a response signal during the 9th clock period;

Each Data byte is before the transmission time (MSB;

Write communication process:

1. When the master node detects that the bus is idle, it first sends a start signal to manage the bus;

2. Send an address byte (including a 7-bit address code and a r/W );

3. When the controlled device detects that the address sent by the master device is the same as its own address, it sends a response signal (ACK );

4. After the master receives the ACK, it starts to send the first Data byte;

5. After receiving the Data byte, the controller sends an ACK to continue data transmission. Sending Nack indicates that data transmission is complete;

6. After the master node sends complete data, it sends a stop to end the entire communication and release the bus;

Read communication process:

1. When the master node detects that the bus is idle, it first sends a start signal to manage the bus;

2. Send an address byte (including a 7-bit address code and a r/W );

3. When the controlled device detects that the address sent by the master device is the same as its own address, it sends a response signal (ACK );

4. After the master receives the ACK, it releases the data bus and receives the First Data byte;

5. After receiving the data, the master sends an ACK message indicating that the data will be transmitted continuously. If the Nack message is sent, the data transmission is complete;

6. After the master node sends complete data, it sends a stop to end the entire communication and release the bus;

Iii. Bus Signal Timing Analysis
1. Idle bus status
The two signal lines SDA and SCL are both at a high level, that is, all devices on the bus release the bus, and their respective pull-up resistors increase their levels;
2. Start Signal

The clock signal keeps the SCL high, and the SDA level of the data signal is lowered (that is, the negative hop is changed ). The start signal must be a hop-and-change signal, and the bus must be idle before the signal is established;
3. Stop the signal
The clock signal keeps the SCL high, and the data line is released, so that SDA returns the high level (I .e. positive hop). The stop signal must also be a hop signal.
4. Data Transmission
During the High-level period, the SDA line must maintain a stable level. The low level indicates 0 (at this time, the line voltage is the local voltage ), the high level indicates 1 (the voltage is determined by the VDD of the component ). The SDA level can be changed only when the SCL line is low.
5. Response Signal ACK
The I2C bus data is transmitted in bytes (8 bits). After each byte is sent, the device releases the data bus during the 9th pulses of the clock, the receiver sends an ACK (which lowers the power of the Data Bus) to indicate that the data is successfully received.
6. No response signal nack
 
The transmitter releases the data bus during the 9th pulses of the clock. If the receiver does not lower the data bus, it indicates an nack. Nack has two purposes: A. Generally, it indicates that the receiver fails to receive data bytes; b. When the receiver is the master controller, it should send an Nack signal after receiving the last byte to notify the controlled transmitter to end data transmission and release the bus, this allows the master receiver to send a stop signal.
7. other signals, such as insertion wait, restart, clock synchronization, bus arbitration, and bus blockout, are not frequently used. For more information, see.

Iv. Addressing conventions
There are two address allocation methods:

1. the IP address of a CPU-included smart device is defined during software initialization, but cannot conflict with other devices;

2. Non-intelligent devices without CPU are solidified by the manufacturer inside the device and cannot be changed.

The 7-bit high is the address code, which is divided into two parts: 1. The 4-bit high is the fixed address which cannot be changed and is fixed by the manufacturer; 2. The low 3 position is the address set for the pin, can be set by external pins (not all devices can be set );

V. Sequence Diagram

Let's look at the data transmission sequence diagram in I2C protocol:

 

In this case, the SCL is the clock, and the SDA is the data. When SDA changes from 1 to 0, and the check mark is 1, data transmission starts. The next seven digits are the device address. Followed by the read/write mark. When it is 1, it is read, and if it is 0, it is write. If there is a device on the I2C bus that corresponds to the requested address, an ACK signal is sent from the device to notify the master device that data can be sent. After receiving the ACK signal, the master device sends an 8-bit data. After the transmission is complete, the check mark is 1, and the SDA is changed from 0 to 1, indicating that the transmission is complete.

 

From this time sequence diagram, we can see that the SCL is very important and the clock edge is well determined. For example, the first seven must be addresses, 8th are read/write marks, data transmission must be 8 bits, and ACK signals must be received.

 

The preceding sequence chart does not indicate the direction of data transmission. Now let's look at the data flow of write operations:

 

The grid is sent by the master device, and the white grid is sent from the device. As shown in the figure, for write operations, the device only sends ack for confirmation.

 

The data flow of read operations is different,

 
At this time, in addition to sending ACK from the device, there is data that follows.