C6748edma_gpio_ interrupted study notes

Apply for EDMA3 Channel

Edma3requestchannel (Soc_edma30cc_0_regs, Chtype, Chnum, Tccnum, EVTQ);

In this function, chnum refers to the application of the channel NUMBER,CC0 and CC1 each have 32 DMA channels, each channel corresponding to a specific event (event), such as cc0 channel6 corresponding to the interruption of GPIObank0

(Guide P439)

(Manual P102)

EVTQ is the event queue, chnum corresponding event, the event will be cached in the event queue, waiting for processing, CC0 has 2 queues, each queue maximum depth of 16, that is, a maximum of 16 events, queue 0 priority is higher than queue 1, if Q1 and Q2 have at least 1 events , the Q1 event will first be out of the team, submit a TR (transfer request) to TR0, and then Q2 the incident to the team, to TR1. When the data transfer is complete, the TC (Transfer Controller) returns TCC (transfer completion code) to the CC (Channel Controller), and the TCC is set in the Param set associated with the channel. The TCC determines which bit in the IPR (Interrupt pending register) is set, and if the corresponding bit in the IER (interrupt enable register) is also 1, enabling the interrupt, a corresponding interrupt is generated to the CPU.

(Guide P522)

Transfer (transfer) completes the resulting specific interrupt event as determined by the following formula.

(Guide P523)

/** \brief Base Address of GPIO memory mapped registers */

#define Soc_gpio_0_regs (0x01e26000)

void gpiobankintdisable (unsignedint baseadd, unsignedint banknumber)

gpiobankintdisable (Soc_gpio_0_regs, 0);

The sentence clears the corresponding bit in the Binten and disables the GPIObank0 interrupt.

(Manual P254)

#define Sys_int_gpio_b0int

Inteventclear (Sys_int_gpio_b0int);

This sentence clears the system interrupt status bits in the DSP interrupt controller, the system interrupt status bit in the event flag register EVTFLAGN of the Interrupt controller (N=1~4), each Evtflag register holds 32 system interrupt states, each one corresponds to an interrupt event, If the EVTFLAG3 1 bits correspond to the interrupt event labeled 65, that is GPIObank0 interrupt, when the GPIObank0 interrupt event occurs, the bit will be set to 1.

(Manual P22)

(Manual P96)

(Mega Handbook P170)

In the interrupt handler (interrupt service routine), the event flag register interrupt event flag bit needs to be cleared, and the corresponding bit write 1 to the event purge register is required. If the GPIObank0 interrupt event occurs, because the interrupt event is labeled 65, the 1 bit of the EVTFLAG2 register will be 1, to clear the bit, you need to write 1 to the EVTCLR3 Register 1 bits.

(Mega Handbook P169)

(Mega Handbook P173)

void Gpiopinintclear (unsignedint baseadd, unsignedint pinnumber)

Gpiopinintclear (Soc_gpio_0_regs, 7);

This clause clears the GPIO interrupt status bits corresponding to the gpiobank0pin6. The Gpio interrupt status register Intstat is a register that flags interrupts on the GPIO pin, and when a gpio pin is interrupted, the bits in the corresponding INTSTATN register are set to 1. The 6 bits of the INTSTAT01 register will be set 1 if the GPIObank0 pin6 is triggered by a falling edge. The software requires 6-bit write 1 to the INTSTAT01 register to clear it.

(Guide P867)

Registering the Interrupt service function

Intregister (C674x_mask_int6, USER0KEYISR);

void Intregister (unsignedint cpuint, void (*USERISR) (void))

{

/* Check The CPU maskable interrupt number */

ASSERT (((cpuint >= 1) && (cpuint <= 15));

/* Assign The user's ISR to the CPU maskable interrupt */

C674xisrtbl[cpuint] = USERISR;

}

staticC674xisr C674xisrtbl[c674x_int_count];

typedef void (*C674XISR) (void);

C674XISRTBL is defined as a function pointer array that holds a function pointer to a function whose parameter list is void and returns a value of void. In fact, C674XISRTBL is the array of pointers that hold the address of the interrupt service program, each pointing to the Interrupt Service program (interrupt service routine) corresponding to the INT4 to INT15. Intregister (C674x_mask_int6, USER0KEYISR); This function points the 6th pointer of the C674XISRTBL function pointer array to the USER0KEYISR function.

The mapping interrupts to the DSP can mask interrupts

Inteventmap (C674x_mask_int6, Sys_int_gpio_b0int);

The sentence function sets the INTSEL6 field of the interrupt multiplexer INTMUX1 to GPIObank0 interrupt event number 65, and the interrupt source labeled 65 is mapped to a CPU interrupt labeled 6. The INTMUXN register address and fields are shown in the following figure:

(Manual P96)

(Mega Handbook P178)

So, when a 65th interrupt (GPIObank0 interrupt) occurs, why is the CPU capable of executing the function pointed to by the c674xisrtbl[c674x_mask_int6] function pointer? The mechanism behind the problem is a bit around, and I've been thinking about it for a long time.

First, when the DSP interrupts the controller initialization,intdspintcinit(), the function interrupts the service table pointer ISTP (Interrupt service table Pointer) points to the interrupt vector table _ Intcvectortable, the function section is as follows:

/* Set Interrupt Service table pointer to the vector table */

#ifdef__ti_eabi__

ISTP = (unsignedint) _intcvectortable;

#else

ISTP = (unsignedint) intcvectortable;

#endif

The intcvectortable interrupt vector table is defined in the Intvecs.asm file of the Systerm_config project in Starterware, with the following code:

1.; 2.;	File:intvecs.asm 3.  
; 4.;	Brief:contains interrupt vector table and fetch packets 5.  
; 6.;	Copyright (C) Texas Instruments INCORPORATED-HTTP://WWW.TI.COM/7. ;	  
All rights RESERVED 8.	9.; ********************************************************** 10.               ;	Global Symbols 11.	    ; ********************************************************** 12.	    . Global _intcvectortable 13.	    . Global _c_int00 14.	    . Global _C674X_NMI_ISR 15.	    . Global _C674X_RSVD_INT2_ISR 16.	    . Global _C674X_RSVD_INT3_ISR 17.	    . Global _C674X_MASK_INT4_ISR 18.	    . Global _C674X_MASK_INT5_ISR 19.	    . Global _C674X_MASK_INT6_ISR 20.	    . Global _C674X_MASK_INT7_ISR 21.	    . Global _C674X_MASK_INT8_ISR 22.	    . Global _C674X_MASK_INT9_ISR 23.	    . Global _C674X_MASK_INT10_ISR 24.	    . Global _C674X_MASK_INT11_ISR 25.	    . Global _C674X_MASK_INT12_ISR 26.	    . Global _C674X_MASK_INT13_ISR 27.	. Global _C674X_MASK_INT14_ISR 28.    . Global _C674X_MASK_INT15_ISR 29.	30.; ********************************************************** 31.               ;	Interrupt Fetch Packet 32.	; ********************************************************** 33.	    Vec_entry. Macro Addr 34.	    STW B0,*--b15 35.	    Mvkl addr,b0 36.	    Mvkh addr,b0 37.	    B B0 38.	    LDW *b15++,b0 39.	    NOP 2 40.	    NOP 41.	    NOP 42.	  
. ENDM 43.	44.; ********************************************************** 45.               ;	Interrupt Vector Table 46.	    ; ********************************************************** 47.	. align 1024 48.	    _intcvectortable:49.	    Vec_entry _c_int00 50.	    Vec_entry _C674X_NMI_ISR 51.	    Vec_entry _C674X_RSVD_INT2_ISR 52.	    Vec_entry _C674X_RSVD_INT3_ISR 53.	    Vec_entry _C674X_MASK_INT4_ISR 54.	    Vec_entry _C674X_MASK_INT5_ISR 55.	    Vec_entry _C674X_MASK_INT6_ISR 56.	    Vec_entry _C674X_MASK_INT7_ISR 57. Vec_entry _C674X_MASK_INT8_ISR 58.	    Vec_entry _C674X_MASK_INT9_ISR 59.	    Vec_entry _C674X_MASK_INT10_ISR 60.	    Vec_entry _C674X_MASK_INT11_ISR 61.	    Vec_entry _C674X_MASK_INT12_ISR 62.	    Vec_entry _C674X_MASK_INT13_ISR 63.	    Vec_entry _C674X_MASK_INT14_ISR 64.  
 Vec_entry _C674X_MASK_INT15_ISR

However, the Intvecs.asm file, the name of the interrupt vector is C674X_RSVD_INTN_ISR (n=2~15), and the C674XISRTBL function pointer array does not have an intuitive connection, how are the two corresponding? For example, when a 65th interrupt occurs, according to the above mapping, the CPU will execute the 6th Block CPU Interrupt Service program _C674X_MASK_INT6_ISR, but where the entrance of the C674X_MASK_INT6_ISR program. I've been looking for a long time, and I finally found the definition of the function in the interrupt.c file, as follows:

#ifdef __ti_eabi__

Interrupt void _c674x_mask_int6_isr (void)

#else

Interrupt void C674X_MASK_INT6_ISR (void)

#endif

{

C674XISRTBL[6] ();

}

Note that this sentence c674xisrtbl[6] (), originally in the Interrupt Service program C674X_MASK_INT6_ISR, the program jumps directly to c674xisrtbl[6] function pointer refers to the function, namely the above registered user function Userisr, This explains how the program can execute to the user's registered function after the interrupt has occurred, and the technical route is a bit around.